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cpandya
Participant
Participant
326 Views
Registered: ‎06-13-2018

BitStream generation fails with Aurora IP with DRC UCO-1 error when IP recompiles

Hello,

I have added Aurora IP in my design with 4 Lanes and starting GT Lane is X0Y8. GT refclk selection is MGTREFCLK0 of Quad X0Y2. I am seeing error while generating binary file. Vivado is throwing error DRC UCIO-1 and when I open placed IO report, I see Lanes are not placed correctly. I see this issue only when I compile Aurora IP every time. If Aurora IP doesn't compile and use cache, then I don't see this error.

cpandya_1-1626369150532.png

 

cpandya_0-1626390919772.png

 

Can anyone help with this?

Thanks in Advance.

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rkhatri
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Moderator
190 Views
Registered: ‎01-10-2019

Hi @cpandya,

It looks like location constraint is not specified for these pins rxn, rxp, txp and txn. 

Thanks,
Rahul Khatri
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cpandya
Participant
Participant
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Registered: ‎06-13-2018

Thanks for reply @rkhatri ,

I am not explicitly writing constraints for these pins. I just mentioned starting GT lane in IP GUI but design doesn't take it according and throws error.
Let me know if I need to do it differently.

Thanks!

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rkhatri
Moderator
Moderator
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Registered: ‎01-10-2019

Hi @cpandya,

Please try to add the constraints for those pin explicitly and see if still errors are seen or not.

Thanks,
Rahul Khatri
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