07-15-2021 10:16 AM - edited 08-04-2021 11:50 AM
I have added Aurora IP in my design with 4 Lanes and starting GT Lane is X0Y8. GT refclk selection is MGTREFCLK0 of Quad X0Y2. I am seeing error while generating binary file. Vivado is throwing error DRC UCIO-1 and when I open placed IO report, I see Lanes are not placed correctly. I see this issue only when I compile Aurora IP every time. If Aurora IP doesn't compile and use cache, then I don't see this error.
Can anyone help with this?
Thanks in Advance.
08-06-2021 12:46 AM
It looks like location constraint is not specified for these pins rxn, rxp, txp and txn.
08-11-2021 12:25 PM
Thanks for reply @rkhatri ,
I am not explicitly writing constraints for these pins. I just mentioned starting GT lane in IP GUI but design doesn't take it according and throws error.
Let me know if I need to do it differently.
08-13-2021 12:24 AM
Please try to add the constraints for those pin explicitly and see if still errors are seen or not.