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pieterwillemen
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Registered: ‎03-23-2016

Block Memory: Use BRAM Controller and Standalone mode at the same time?

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Hi,

 

In my project I have an IP core ('zigbee_fft') that generates some output. I would like that the Zynq ARM processor is able to read this output. I prefer not to use a FIFO and AXI DMA, as this makes things much more complicated. So I was thinking, that I could use a Block Memory Generator for this. I want my ('zigbee_fft') core to WRITE values into port B of the Block Memory and then connect port A of the Block RAM to the Zynq procesor via an AXI_BRAM_CONTROL and an AXI_Interconnect, so that that the processor can easily READ these values using simple addressing. To do this, I set the 'Operating Mode' of the Block Memory Generator to 'BRAM Controller' in IPI, hoping that I can still interface with port B manually. Please see figure 1 below.

 

 BMG_two_modes.png

 

I have spent a lot of time designing this. Synthesis completes successfully and I have also completed my C code design in SDK. However, when testing the design, I meet the following problem: I am able to read and write values from and to the Block RAM from the processor, however no values seem to be written by my own core. All values simply remain zero, if I do not write anything from the processor side.

 

In figure 2, you can see what the output signals of my core look like, these should be allowing to write to the Block Memory, I think.

 

 port_B_write_signals.png

 

-Do you think there is a problem with my output signals to write data to the core?

-Is it possible to connect to a Block Memory using a BRAM controller on one port and manual signals, using the other port?

-Do you have any other suggestions on how I could achieve what I want to do here?

 

Thank you very much!!

 

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pieterwillemen
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Registered: ‎03-23-2016

Hi!

 

I have been able solve this issue. It turns this is most certainly possible. All I forgot, was to connect a clock to port B. I thought I had connected all pins of port B, but there was still a '+' sign, as you can see in the figure, and when clicked upon this made a clock available for port B. For me, this actually should be considered a bug!

 

Everyting works corectly. I am using version 2014.2.

 

Kind regards.

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pieterwillemen
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Registered: ‎03-23-2016

Anyone? I really need help! I have tried everything I know...

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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi @pieterwillemen

 

I dont think this is allowed (have AXI BRAM controller on one side and custom IP on other side)

 

Which version of Vivado are you using? Is the block design validation succesful?

 

Can you write the BD TCL using write_bd_tcl command and upload the same here?

Thanks,
Deepika.
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pieterwillemen
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Registered: ‎03-23-2016

Hi!

 

I have been able solve this issue. It turns this is most certainly possible. All I forgot, was to connect a clock to port B. I thought I had connected all pins of port B, but there was still a '+' sign, as you can see in the figure, and when clicked upon this made a clock available for port B. For me, this actually should be considered a bug!

 

Everyting works corectly. I am using version 2014.2.

 

Kind regards.

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jg_spitfire
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Registered: ‎12-10-2019

hi, could you tell me please what config did you apply to the axi interconnect block to set those two arrows (yellow and blue) ?, and is it necessary?, some tutorials don't have that block in that way and I am confused

2.- do you understand why do you need to put 1111 in wea?, I mean, do you know why do we need a vector and not a bit?

and the last question, were you able to simulate all the blocks or just generated the signals for your custom ip core and the bram?

thanks

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ronnywebers
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Registered: ‎10-10-2014

@jg_spitfire the '1111' in wea is because each bit enables one byte in the 32-bit lane. The BRAM allows to select which bytes you write

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