06-11-2018 01:02 AM
Hello Xilinx community,
currently I'm working on a project, which requires reading from/writing to a Block Memory.
The Block memory obtains the following key features:
I'm currently struggeling with two major porblems:
Hopefully you can help me out with this matter!
06-13-2018 10:49 PM
thanks for your quick reply. I've done so and it says that this port is undefined. So it seems there is still a functional problem within my module. I will check this out.
Are there any hints regarding my first question, related to the Address Mapping?