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h89w43hilz
Observer
Observer
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Registered: ‎05-22-2018

Block RAM AXI4: Base address + ARREADY signal

Hello Xilinx community,

 

currently I'm working on a project, which requires reading from/writing to a Block Memory.

The Block memory obtains the following key features:

  • Block Memory Generator V8.4, created by IP catalog (not IP Integrator!!!) used on a XC7K325T FPGA
  • AXI4 interface as Memory slave + Simple Dual Port RAM
  • Port width = 64 bits, Port depth = 512

I'm currently struggeling with two major porblems:

  1. As I'm using the Block RAM with in-built AXI4 interface, I'm not able to use the IP Integrator, except I would create and package my design to an IP core. So I am not able to get the Address Editor to specify the Base address, as no block design is possible. When not using the block design, am I able to define a base address on my own, using a header file? If yes, are the any documentations or examples out there, which describes the format of such a header file?
  2. I've tried to simulate the block memory to understand the AXI4 interactions. According to the manual (Section AXI4 Incremental Burst), the write operation executes as expected. The behaviour of the read operation is not as expected, because the ARREADY signal remains in the X-state, which is the thing I do not understand (see attached image). From my knowledge the ARREADY signal is used to signalise to the master that the BRAM is ready to accept the read address and associated control signals. Is it related to a mismatched base address or is there another misbehaviour in my simulation, which I don't takt into account?BRAM_ARREADY_Xstate.png

Hopefully you can help me out with this matter!

 

Kind regards,

h89w43hilz

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2 Replies
zyanwu
Observer
Observer
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Registered: ‎12-14-2013

Right click on the signal -> Report Drivers and check if you have multiple drivers or any signals that are contributing to arready are X or Z

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h89w43hilz
Observer
Observer
1,115 Views
Registered: ‎05-22-2018

Hello zyanwu,

 

thanks for your quick reply. I've done so and it says that this port is undefined. So it seems there is still a functional problem within my module. I will check this out.

 

Are there any hints regarding my first question, related to the Address Mapping?

 

Kind regards,

h89w43hilz

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