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Explorer
Explorer
3,485 Views
Registered: ‎03-31-2016

Block RAM byte-write issue

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Hello

 

I want to used Block RAM and bit-write, but xilinx only support byte-write(8-bit/9-bit)

 

Have any method can implement bit-write(1-bit)?

 

FPGA device: xc7v2000

Software: Vivado 2015.4

 

Block RAM.PNG

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Xilinx Employee
Xilinx Employee
6,169 Views
Registered: ‎08-01-2008

Re: Block RAM byte-write issue

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core only supports bye write enable option for 8/9 bits

For other option please find details in core product guide
https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_0/pg058-blk-mem-gen.pdf
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
6,170 Views
Registered: ‎08-01-2008

Re: Block RAM byte-write issue

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core only supports bye write enable option for 8/9 bits

For other option please find details in core product guide
https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_0/pg058-blk-mem-gen.pdf
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
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Visitor mianni
Visitor
3,396 Views
Registered: ‎09-21-2015

Re: Block RAM byte-write/read issue

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Hi! I do wonder about the byte read/write functionality with single port ram with spartan 6. Ram is write first mode. 

LogiCORE IP BMG v7.3 is used.

The challenge is to do the read operation from ram. The ram is accessed via an address-decoder RTL-provided.

 

Byte write of datamem is connected to byte-select ( s_dmem_o(0).sel_o) of address-decoder.

It seems there are two ways of reading ram from datasheet PG058 December 18, 2012. One way is to force write enable to zero or manipulate enable (EN), reset (RST), and register enable (REGCE) pins for controlling data-flow out.

 

But is there any way to select readout of more than one byte at the time?  Right now it seems that only byte read is the default

 

This is the instantiation of datamem up to address-decoder:


     dat_o =>s_dmem_i(0).dat_i,---- connect to address_decoder
    dat_i =>s_dmem_o(0).dat_o,
    adr_i => s_dmem_o(0).adr_o,--
    wre_i => s_dmem_o(0).sel_o,-- connect for byte(3 downto 0)
    ena_i => s_dmem_o(0).ena_o, --connect up to address_decoder logic
    clk_i =>wb_i.clk_i

 

 

Regards!

read_datamem.JPG
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