I tried to infer a byte-write block RAM (32*8192 bits) with Vivado 2014.4 and initialize some of the data content(please see the attachment). The simulation runs correctly. However, after the bitstream file is generated and downloaded to FPGA board(KC705), I examined the data memory content by the logic analyzer, all the memory content become zero. Has anyone encounter the same problem? Any suggestions or comments would be highly appreciated!