I probably posted this in the wrong forum initially, please pardon my repost. Original post is below
http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Block-RAM-latency-is-10-clocks-in-simulation-should-be-1-clock/td-p/337145
In simulations I am seeing the Block RAMs take 10 clock cycles to return data. I am using Vivado 2013.2 with a Kintex-7 and Block RAM generator 8.0. The IP Catalog output claims that the latency should be 1 cycle. The attached waveform is the 10 cycle latency we see in simulations. I haven't probed the signals within the FPGA with the ILA yet but I am seeing an identical failure from simulation on the output of the FPGA where we send out the wrong data due to the slow timing.
I saw an almost identical post way back in 2009 but the previous poster's resolution doesn't fix the behavior I'm seeing. The previous poster had mistakenly set the clock period to 10ps instead of 10ns, but as you can see in this waveform I have 10ns clock periods.
( http://forums.xilinx.com/t5/Virtex-Family-FPGAs/BRAM-read-latency-too-long/td-p/31126 )
Any ideas?
