Block RAM with 1 writer and 2 readers with different clocks
I have a project that uses the GTP Transceiver to send and receive data at 2.970 GHz with a TX (xmitClk) and RX (recvClk) clock rate of 148.5 MHz. The TX or RX clock (depending on whether it is a master or slave system) is then used with an MMCM to generate 196.608 MHz for audio processing (audioClock). I am using block RAM to store data received on the GTP port. This data then needs to be sent again on the GTP transceiver and also accessed by other subsystems running with the audio clock.
This means there are essentially 3 types of access to the BRAM:
Write using recvClk and data received on the GTP port
Read using xmitClk for transmit on the GTP port
Read using audioClk for other processes
The recvClk (write) and xmitClk (read) processes run at the same time, but are guaranteed to not have conflicting addresses. The audioClk (read) is guaranteed to not run at the same time as the recvClk (write), by time multiplexing the operations and ensuring they are scheduled to not conflict.
The problem I am having is figuring out how to have essentially two separate read processes accessing the BRAM. I could probably ensure that only one of them is accessing it at a time, but it seems that multiplexing clocks is a bad idea.
The one thought I have, is using 2 BRAMs and storing the same values to both. Then having the individual read processes be dedicated to their own BRAM. It seems like this would work, but I wanted to see if anyone has a better idea.