11-12-2019 03:12 AM - edited 11-12-2019 03:27 AM
I am using block memory generator 8.4 to instanciate a true dual port ram in stand alone mode over an ultrascale device(XCZU3EG).
I am using a bram axi controller in port A and user defined in port B. I simulate the design with modelsim and the write and the behaviour of the FSM that I am using to write work properly. But when I generate the binary files I neve see nothing written in the memory. I always can write and read from the port that is connected to the mpsoc but never with the FSM.
What could it be the problem?.
Find attached also the captures of configuration.
11-12-2019 08:59 AM - edited 11-12-2019 09:00 AM
The first debugging step should be to add bebug probes and monitor if proper transactions happening on below signals or not
11-12-2019 09:22 AM
11-12-2019 09:25 AM
11-12-2019 09:51 AM
11-12-2019 11:43 PM