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Vasundhara19
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Registered: ‎03-22-2020

Block memory using IP catalog in Vivado

Hello,

I am new to creating IP using Xilinx Vivado.

I have a .coe file that contains image pixel data in hexadecimal format. I attached the .coe in IP catalog->Other options->Memory initialization(as shown in image 1) and created a block memory(single port RAM).

Now, I have two questions: 1. where can I find the .coe file data in the block memory I created, how can I access the address locations where my data is stored and

2. Why is the block memory created in VHDL when I selected my target language as Verilog.

Thanks.

 

 

image1.PNG
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pthakare
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Registered: ‎08-08-2017

Hi @Vasundhara19 

#1 The data is stored from address "00"

e.g first entry in your .coe file corresponds to data at first address .

After the initialization you can check cell properties once sythesis or implementation is completed , Look of INIT_XX 

#2  The source files for block memory generator are encrypted and you can only have wrapper file in VHDL , but the instantiation is available in verilog as well as VHDL.

Go to sources - IP-> instantiation files , you can find two files there , each one corresponds to VHDL and Verilog instatiation.

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Vasundhara19
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Registered: ‎03-22-2020

Thanks.

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