03-13-2020 05:05 PM
I expect the 3F03F851 to appear on Doutb 1 clock cycle early (true dual port ram, no output register, common clock, write first, always enabled)
It does not appear in the same cycle , it does not appear in the next cycle, it appears on the 3rd cycle.
clock cycle 1 : 3F03F851 is written to bram address 101 (red circle) clock cycle 3: Data output is 3F03F851 (yellow circle)
03-14-2020 05:11 AM
The Data is read 1 clock after writing. The red circle is not around a rising edge. The write occurs at 9090ns, and read at 9100ns.
03-14-2020 10:57 AM - edited 03-14-2020 11:01 AM
@richardhead thanks for your input.
if the first rising edge clock that write en is 1 : is at orange rising edge clock , then
the first rising edge clock that read data is available : is at pink rising edge clock
still 2 clock cycles. or am I reading this wrong?
I started this post since : I am writing data to a memory in the first clock cycle (keeping the read address same with write address), in the second clock cycle I use the read data and do another operation, and the result is wrong.
03-15-2020 04:56 AM - edited 03-15-2020 05:03 AM
what I have (1ST SCREENSHOT because I use 7 series, True Dual Port Ram, Port A : Write First)
According to first screenshot from https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
if I write DIA to Port A then resulting data out port B is X
what I want (2ND SCREENSHOT, correct for SDP)
According to second screenshot from https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_4/pg058-blk-mem-gen.pdf
if I write DIA to Port A then resulting data out port A is DIA
03-16-2020 11:19 PM
I have SR for this issue , As mentioned on SR mail thread
The write mode attribute can be individually selected for each port. WRITE_FIRST outputs the newly written data onto the output bus.
Here you can see the input data is simultaneously written into memory and stored in the data output (transparent write).
Please refer to UG583 https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf page 13 for Write modes.
The below table shows the resulting data out PORTA/B when there is address collision.
i.e when you have true dual port memory configured and Write mode of PORT A is set to Write first , and Write mode of Port B is Read_first/write_first/no change
In the configuration if you are trying to write from PORTA and read from PORTB , the resulting Data out PORTA is DIA as per above timing diagram and resulting Data out PORTB is “X”
Now coming to your question ,
While reading from memory , this write modes don’t have any significance , with no output register selected , you should get the data out after one clock cycle.
03-27-2020 09:32 PM
The resolution is already provided to customer on service request .
Here is the resolution for your information
when I checked the XCI , you have collision warning selected for structural simulation and disable collision warning for behavior simulation.
Looking at the below capture you are trying to write and read from address “101” and hence it is read-write collision.
In this configuration write will be successful but data on output B after inherent latency will be “X” and in next clock cycle there is no address collision and you will be getting data at address “101”
After one clock cycle inherent latency .
So looking at the overall picture it is 2 clock cycle latency in case of address collision and it is correct behavior.
I will recommend you to re-run the simulation with collision warning selected to ALL or Generate “X” only for structural simulation and don’t disable the collision warning for behavioral simulation to observe the “XXX” in output during write-read collision.
Customer have tried this and observe the behavior expected.
first clock cycle XXX, 2nd clock cycle correct data on PortB doutB