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Observer
Observer
13,338 Views
Registered: ‎07-13-2011

Bug in FIFO generator v10.0?

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Hi all,

 

In my design I am using the FIFO generator v10.0, but I have an issue simulating this. When something is written into the FIFO, the data that is present before the wr_en-cycle is written into the FIFO. So if the data changes simultaneously with the wr_en on the wr_clk then the data before the wr_en-cycle is written. This only appears when I am using the vhdl-model and if I use the verilog-model everything goes fine.

Does anybody have an idea of what I am doing wrong?

 

Thank you for your help.

 

Regards,

 

Danny

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Observer
Observer
19,759 Views
Registered: ‎07-13-2011

Hi,

 

I've upgraded tot fifo generator V11.0 and now the problem suddenly disapeared so now I can move on again.

 

Thanks for the suggestions.

 

Regards,

 

Danny

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Xilinx Employee
Xilinx Employee
13,329 Views
Registered: ‎07-11-2011

Hi,

 

Looks like an issue with core, can you share the simulation waveforms and .xco please?

 

Regards,

Vanitha.

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Observer
Observer
13,322 Views
Registered: ‎07-13-2011

Hi,

 

Here you go! I've added two waveforms:

 

1. VHDL model

2. Verilog model

 

Same testbench, same simulator, only difference is the modeltype (VHDL vs. Verilog)

 

Regards,

 

Danny

fifo vhdl.png
fifo verilog.png
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Xilinx Employee
Xilinx Employee
13,295 Views
Registered: ‎07-11-2011

Hi,

 

If you could crop the image and zoom the signals of interest at the wrong data portion the image would be seen clearly.

Is it post synthesis/post implementation simulation?

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Observer
Observer
13,283 Views
Registered: ‎07-13-2011

Hi,

 

This is behavioral simulation.

 

As you can see, the first data package that is written into the FIFO, doesn't come out when the data in the FIFO is read.

 

Regards,

 

Dannyfifo write.pngfifo read.png

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Xilinx Employee
Xilinx Employee
13,253 Views
Registered: ‎08-01-2008
I would like if you can reproduce this issue with provided test bench Test bench generated with core generation. Issue can be with how the stimulus drive by your test bench. You may introduce transport delay in data path.
Thanks and Regards
Balkrishan
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Observer
Observer
13,224 Views
Registered: ‎07-13-2011

The thing is that it works just fine if a test it stand alone.... But in my testbench it seems that it doesn't process the first write for some reason.

 

You mentioned something about introduction of transport delay in data path... How can I check if I did?

 

Regards,

 

Danny

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Xilinx Employee
Xilinx Employee
13,180 Views
Registered: ‎08-01-2008
you need to make sure data, address and control signal should not assert at same time
Thanks and Regards
Balkrishan
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Observer
Observer
19,760 Views
Registered: ‎07-13-2011

Hi,

 

I've upgraded tot fifo generator V11.0 and now the problem suddenly disapeared so now I can move on again.

 

Thanks for the suggestions.

 

Regards,

 

Danny

View solution in original post

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Xilinx Employee
Xilinx Employee
13,104 Views
Registered: ‎08-01-2008
yes this issue got fixed in V11.0 version
Thanks and Regards
Balkrishan
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