Built-in FIFO reset - how long must be WREN and RDEN low before asserting RST?
I want to implement in my design the possibility to reset a FIFO of type Built-in FIFO by asserting a synchronous reset signal on the asynchronous reset input. The clocks are not really independent as the read clock has the double frequency of the write clock but the core is generated with a "independent clock" policy.
When simulating this I received warnings because of the WREN and RDEN signals being asserted during reset, although they were low when asserting RST. So I figured out these signals are somehow delayed internally and I delayed assertion of RST with respect to the last assertion of WREN or RDEN.
Now I am at 18 WR_CLOCK delay cycles that have to pass without the WREN and the RDEN signal being asserted to prevent the simulation model from generating warnings. This seems quite much to me and I can't find a specification in the UG175 how long the time interval shall be between the last assertion of one of the signals and assertion of the RST signal.
So is the simulation model too pessimistic here or do I really have to keep this time interval of 18 WR_CLOCK cycles?