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anderson1008
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Registered: ‎10-18-2012

CAM (xapp1151) Simulation under ModelSim 6.6

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Dear expert,

 

I have added the example design of the content addressable memory in ISE 13.4. The simulator I use is ModelSim 6.6. I successfully simulated the project with different configurations using Block RAM-based implementation.

 

When I use SRL-16E-based implementation, I also get the expected results, except a little bit delay on the output. According to the document file (xapp1151: page 7), "The SRL 16E-based CAM asserts the MATCH signal on the first rising clock edge after data is placed on the DIN bus......). However, in my case, there is a 2ns seconds delay as the clock is 20ns after data is placed on the DIN bus.

 

The following is a screenshot of my simulation result. As you can see, at 115 ns, the input data was provided on the cam_din bus on the negative edge of the clock; at 125 ns, the positive edge clock arrives; the output  is ready at 127 ns, instead of 125 ns.

 

Screenshot_CAM_OutputDeday.JPG

 

Since there is no delay added in my simulation script, why do I have that 2ns delay? ModelSim do not take the path delay into consideration, right? (I did not change the delay model of the ModelSim.)

 

I appreciate in advance if someone can help me about this issue.

 

P.S. A image with better quality is attached.

 

Screenshot_CAM_OutputDeday.JPG
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gszakacs
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Registered: ‎08-14-2007

Its strange that I just answered a very similar question in this thread.

 

Basically, the issue is simulation models.  The SRL16 and other unisim models

contain some timing delays that show up in behavioral simulation.  Any behavioral

HDL that does not include unisim models or have explicit delays in the HDL will

have no delay from the clock edge.

 

-- Gabor

-- Gabor

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gszakacs
Professor
Professor
16,168 Views
Registered: ‎08-14-2007

Its strange that I just answered a very similar question in this thread.

 

Basically, the issue is simulation models.  The SRL16 and other unisim models

contain some timing delays that show up in behavioral simulation.  Any behavioral

HDL that does not include unisim models or have explicit delays in the HDL will

have no delay from the clock edge.

 

-- Gabor

-- Gabor

View solution in original post

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anderson1008
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Registered: ‎10-18-2012

Dear Gabor,

 

Thanks for you quick reply.

 

I think I understand your point. In another word, it will not only happen in this TCAM project, but also every other projects when the simulator references the components in Unisim library in which the functionality of certain primitives (such as SRL-16) is defined. Virtually, it is a normal phenomena in a behavior simulation when a device-specific primitive from Unisim library is instantiated in the code.

 

Am I right?

 

- Anderson

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gszakacs
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Professor
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Registered: ‎08-14-2007

That's pretty much correct. Other Xilinx library models may also have delays. You can see the source for the library models under:

 

<install_dir>/ISE/<Verilog|VDHL>/src/<library_name>

 

For example, on my machine:

 

F:\Xilinx\13.4\ISE_DS\ISE\verilog\src\unisims\SRLC16E.v

 

-- Gabor

-- Gabor
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