05-01-2020 12:14 PM
I used a ZC706 board as a CPRI master, and it worked well. No I have ported the code to an Ultrascale+. I have a few errors on the HDLC link, so I have looked at the hdlc_tx_enable and hdlc_rx_data_valid signals on the scope. During 10 milliseconds they behave as expected (depending on the HDLC rate), then during 10 milliseconds they are constant zero, then again they behave as expected, ...
Thank you for your help
05-19-2020 11:11 PM
Please try to run CPRI hardware demo design.
05-27-2020 04:00 AM
06-18-2020 05:55 AM
Sorry for my late answer. I would prefer not to start from the demonstration design, because on the other side of the CPRI link my design is working well, and the demonstration design is quite different from mine.
I have 2 boards linked by CPRI. The clocks synchronize well. The "Status Code and Alarm Register (0x0)" reads alternatively 0x0F and 0x11 on both sides, if I try to read every 10 ms (my reading is not perfectly synchronized). As written above, on the scope it seems that everything is good for 10 ms, then the link is down for 10 ms, alternatively. I can exchange HDLC data, when I am lucky.
06-18-2020 06:36 AM
I have output some debug signals. On the attached scope image,
So arround the end of a 10 ms chunk, I see local_lof, local_rai and stat_alarm high.
06-18-2020 07:53 AM - edited 06-18-2020 07:56 AM
I have changed my debug signals. Channels 0 to 7 are from the CPRI slave, 8 to 15 are from the master.
and similarly from 8 to 15 for the master. So the local_lof and local_rai appears first on the slave side. Nevertheless it seems that the link works well for 10 ms. And my slave board works well with another master.