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msjatxilinx
Adventurer
Adventurer
9,492 Views
Registered: ‎03-27-2013

Cache Implementation without Processor

How can I implement a cache memory for look-up purposes which works with my custom logic, not Microblaze or PPC or ARM?

I have implemented different cache architectures using VHDL or Verilog, but they cannot afford my performance requirements. On the other hand Microblaze has cache option. This means that there should be a way which implements an efficient cache memory. If there was an IP like SDRAM or DRAM, etc it would be nice; nonetheless it seems there is no such option.

 

How could I instance a cache memory using Xilinx/FPGA features which communicates with my custom logic?

Please keep in mind that there is no Microblaze or PPC or ARM processor.

 

Thanks

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balkris
Xilinx Employee
Xilinx Employee
9,157 Views
Registered: ‎08-01-2008

I am not sure what is your application. You can use distributed or block memory for cache design.
Thanks and Regards
Balkrishan
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