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zhch777777
Participant
Participant
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Registered: ‎10-27-2017

Can clk_wiz use discontinuous clock?

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Normally, the PLL is connected to a continuous clock. But I have a discontinuous clock that needs to track the phase. Can I use fb_out to generate a clock input corresponding to the edge to fb_in? Does the PFD in the PLL only examine the phase relationship between the two clock edges? or Still require a duty cycle.thanks

 

 

无标题1.bmp
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karnanl
Xilinx Employee
Xilinx Employee
530 Views
Registered: ‎03-30-2016

Hello @zhch777777 

No, a specific duty-cycle is required for both PLL/MMCM.
It is written in the datasheet of your device. ( Please read the datasheet).

For example this spec is for Kintex UltraScale+ (DS922)
MMCM_DUTY.jpg



Regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
531 Views
Registered: ‎03-30-2016

Hello @zhch777777 

No, a specific duty-cycle is required for both PLL/MMCM.
It is written in the datasheet of your device. ( Please read the datasheet).

For example this spec is for Kintex UltraScale+ (DS922)
MMCM_DUTY.jpg



Regards
Leo


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

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View solution in original post

zhch777777
Participant
Participant
504 Views
Registered: ‎10-27-2017

thanks.

 i had seen a PFD  design as shown below。Is PFD in PLL like this ? Or XOR gate design。

 

pIYBAFtzx5aAN_5-AAB6b5XRTh0731.png
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karnanl
Xilinx Employee
Xilinx Employee
493 Views
Registered: ‎03-30-2016

Hello @zhch777777 

Pardon me but we do not provide silicon architecture information at this level details.

If you do not follow clock-duty spec mentioned in the datasheet, your FPGA design may not work.

Kind regards
Leo


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