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Visitor
Visitor
2,403 Views
Registered: ‎07-01-2017

Can't findout by component inst.. code which one dram bram or what ? And how to do these/.

Dear All , i am new in FPGA VHDL.

Who can tell me what is this product code for ?  In bram there impossible to make  different address and data width. addra and addrb must be same , and dina with doutb also must be same , what are strange thing is it ?  Code taken from https://github.com/daveshah1/CSI2Rx ..

  COMPONENT input_line_buffer
    PORT (
      clka : IN STD_LOGIC;
      ena : IN STD_LOGIC;
      wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
      dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
      clkb : IN STD_LOGIC;
      addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
      doutb : OUT STD_LOGIC_VECTOR(255 DOWNTO 0)
    );
  END COMPONENT;

  COMPONENT output_line_buffer
    PORT (
      clka : IN STD_LOGIC;
      ena : IN STD_LOGIC;
      wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
      addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
      dina : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
      clkb : IN STD_LOGIC;
      addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
      doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
    );
  END COMPONENT;

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1 Reply
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Explorer
Explorer
2,396 Views
Registered: ‎04-12-2017

I don't know for each and every Xilinx device, but for MPSoC it is definetly possible to have different read and write data bus width for BRAMs. Since you have to be able to access all memory from both ports, 2^addra_w x dataa_w must be the same as 2^addrb_w x datab_w

 

In your case it is OK:

 

2^12 x 64 = 2^10 x 256

Avi Chami MSc
FPGA Site