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Registered: ‎08-09-2018

Can't write to Ultra RAM - Block Design IPs

Dear Sir or Madam,

It seems like we have issues writing the URAM.

We are working on KCU116 Eval board using the block design option on Vivado.

In order to set the URAM I have added an AXI BRAM Controller with the following settings:

  1. AXI proocol - AXI4
  2. Data Width - 64
  3. Number of BRAM interfaces - 1
  4. Enable ECC - no

*All the other options are greyed out.

In addition to the BRAM controller I have added a Block Memory Generator with the following settings:

  1. Mode - BRAM Controller
  2. Memory Type - Single Port RAM
  3. Select the Primitive Type to be Used - URAM
  4. Sleep - not selected

*All the other options are greyed out.

At the address editor I have set the URAM for 1M with offset address of 0x0800_0000 (up to 0x80F_FFF)

Pressing "Validate Design" presented the following warnings (no error or critical issues):

  • [BD 41-721] Attempt to set value '64' on disabled parameter 'Read_Width_A' of cell '/axi_uram_ctrl_0_uram' is ignored
  • [] /axi_uram_ctrl_0_uram Block Memory Generator IP is configured to use UltraRAM, but UltraRAM does not support Memory Initialization, hence elf association or Initialization of the memory through .coe or .mem  files is not possible

*seems like the second warning is less relevant

Right after validation I have done the followings:

  1. Generate Block Design
  2. Run Synthesis
  3. Run Implementation
  4. Generate Bitstream 
  5. Burned the EVAL BOARD

Using the SDK we were tryng writeing the URAM unseccessfuly, but we did managed to write the BRAM and the DDR.

Please note:
To generate 1MByte of URAM on 64 bit width (8 byte) means that I need to use 128K depth.
In order to do so the following should accour:

  1. addra (address port A) should be 17 bit [16:0] (128K) - Block Memory Generator shows [31:0]
  2. AXI BRAM Controller bram_addr_a shows [19:0] - doesn't match the Block Memory Generator addra

By the way, trying to open the IP Example Design of the Block Memory Generator presented the following error:

  • [Common 17-69] Command failed: Unable to open example project; see previous messages.

*no previous messages were presented

So my questions are:

  1. Any Idea on how to fix it using the block design?
  2. We are using the MicroBlaze (10.0) processor which is 32bit. does the AXI interconnect knows how to convert the data from 32bit to 64bit to the BRAM controller? I assume it does.

Refael Torika

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Registered: ‎08-08-2017

Hi @torikar 


Refael have file a Service request on this SR and it is resolved by

" URAM was connected to the AXI interconnect on the DC bus of the MicroBlaze instead of the DP or IP AXI interconnect bus"


@callmejacklogan  Is it possible you to share your design? How are writing and reading through URAM ? Did you try with mwr and mrd commands ?







Reply if you have any queries, give kudos and accept as solution
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