Can you infer a FIFO

[jff118]

I have been searching all over to try and see if there is a way to INFER a FIFO and what the limitations are if any on devices.

I found AR46515 titled " 7 series FPGA ..... How to infer the use of BRAM and FIFO primitives" 

It calls out UG627 - which does not support 7 series.

Then is points to the libraries guide which specifically says you cannot INFER a FIFO.

So which is it?

I wrote a generic  BRAM module a while ago that will succesfully infer all the various Xilinx BRAM options ( single, dual, true dual).

I would like to do the same thing for a FIFO.  Currently it infers the BRAM, but all the address and flags are in LUTS,FFs

Is there a way to INFER a SYNC and or ASYNC FIFO in Vivado?

Thanks for the help

JoeF

[pthakare]

Hi @jff118 

If i understood correctly , you mean to infer a Built in FIFO using your own RTL.  (FIFO36/FIFO18 Primitive).

No , there is no way to infer the built in FIFO, and the only way is 

1. Direct primitive instatiation of FIFO36/FIFO18

2. Use FIFO generator IP

The Common Clock or indepenedent clock block RAM based FIFO can be infer using XPM_FIFO_SYNC and XPM_FIFO_ASYNC Macros documented in UG974.

There is no product revenue for Synthesis tool to infer the Built in FIFO and we have other altenative i.e direct  instatiation or FIFO generator usage.

[avrumw]

I agree with what @pthakare said.

That being said, if you do need to infer a FIFO in a technology agnostic way, you can write it yourself. The BRAM (which is the heart of the FIFO) can be inferred from synthesis. However, the control logic, including the full/empty generation and the clock crossing logic would have to be written in RTL. The resulting code is fully synthesizable and technology independent, but will not get mapped to a FIFO18/FIFO36; the RAM will be mapped to a RAMB18 or RAMB36, and the control logic will be implemented using fabric resources.

Avrum

[jff118]

I understand there is no revenue but it wouldn't be that hard to have an example, COPY THIS and we will infer a FIFO so you don't have to use either of the two inadequate solutions you proposed.

Its a bit cumbersome to use the FIFO generator everytime I want to change something.

I have never used a MACRO before but just spent the last two hours trying to understand why Vivado 2018.2 cannot find the Macro Instance Name even though I copied and pasted a piece of example HDL from Xilinx Docs.

I stumbled across another forum post that pointed to AR67815 that says you must first ENABLE the XPM_LIBRARY, which is not documented ANYWHERE.  The AR goes on to say its all listed in the libraries guide, but there is no mention of any library anywhere.  The AR was for 2016.x so I guess this bug has slipped through that cracks for the last 2+ years.

[jff118]

Thanks @avrumw

I already have something like that but was wondering if there was a way to INFER an actual FIFO36 without using COREGEN

[pthakare]

Hi @jff118 

Direct instatiation and FIFO gen usage are only the option.  Do you have further queries around this ? If not please spare a moment to mark the helpful post as accepted solution