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Registered: ‎05-22-2018

Cannot connect a single ended signal to tx_core_clk in JESD204B PHY example design

Hi everyone,

 

I am working with Vivado 2018.2. I opened the JESD204B PHY example design after customizing it. I now try to connect an output clock from clock wizard to tx_core_clk port of JESD204 PHY. I get a DRC -REQP1 error saying the port tx_core_clk is driven by an invalid load.

I ma effectively trying to give a clock that needs to be supplied externally, from the clk wizard. The clk wizard is using si570 clk as input and I ma using it in PLL mode.

 

Can someone suggest how do I solve the problem?

 

Thanks in advance,

 

 

-krishnachandrasekhar100

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Registered: ‎08-21-2007

Is it ok when the tx_core_clk is driven by external pin?

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Registered: ‎05-22-2018

Hi @kren ,

 

So I need to explain something before giving a straight answer.

As I mentioned in the original post, I am working with JESD204 PHY example project. In the example project, under the top module, the tx_core_clk is actually seen to be given from a IBUFDS whose inputs are tx_core_clkp and tx_core_clkn(both are external input ports from the top module) while the output is tx_core_clk.

I am not as familiar with Verilog as I am with VHDL. Hence because the example for JESD204B PHY generates only in Verilog, I had to instantiate this jesd example into a new top module(new source file written in VHDL), where I connect most of the ports of the top module to the input ports of the jesd example instance.

Hence the ports would look like

jesdphy_top_module_diag.png

When I map the tx_core_clkp and tx_core_clkn pins, I get the driven by invalid load error again.

So no, it is not ok when driven by external pin, if this is what you are asking for.

Can you suggest something to solve this?

 

Thanks in advance,

 

 

-krishnachandrasekhar100

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