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Registered: ‎05-22-2018

Cannot find some IPs in Vivado 2018.2

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Hi everyone,

 

I am currently working with the JESD reference design KCU105_AFE74xx_XCVR_2x44210_7p3728G. However the Block design consists of IPs from Vivado 2016.1. I tried opening the project using Vivado 2018.2 (which is the version we are using). It talks about the major upgrades for IP blocks and etc., I would like to be able to port the reference design to Vivado 2018.2

I tried creating the block design again from scratch but I see the following IPs from the reference design not being there in Vivado 2018.2 IP repository

1.iobufs_ti_v1_0
2.leds_v1_0
3.transport_layer_afe768x_44210_0

Edit 1: I was able to find the following IP blocks in the reference design and added them to the block design after adding a repository path to the repository manager

1.iobufs_ti_v1_0
2.leds_v1_0

However I still cannot find 'transport_layer_afe768x_44210_0' IP block. Can Xilinx provide support for this matter?

 

Thanks in advance,

 

 

-Chandrasekhar DVS

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Registered: ‎11-09-2015

HI @krishnachandrasekhar100 

It seems that you were able to get the answer on TI forums:
https://e2e.ti.com/support/rf-microwave/f/220/t/939496 

In general you need to check with the provider of the design for this type of question


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @krishnachandrasekhar100 

It seems that you were able to get the answer on TI forums:
https://e2e.ti.com/support/rf-microwave/f/220/t/939496 

In general you need to check with the provider of the design for this type of question


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Registered: ‎05-22-2018

Hi @florentw ,

Because it involves vivado 2016.1 reference design I thought you could provide support for that. However the .v files were there and I used custom IP generator on Vivado 2018.1 to replicate that block.

 

Thanks anyway,

 

-Chandrasekhar DVS

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Registered: ‎05-22-2018

Hi @florentw ,

 

So I have been trying to create a custom IP using the .v file TI referred, on vivado 2018.2. I am referring UG1118 for that. So the .v file TI used to create the IP block also consists of the dds compilers as a part of the top module. When I try to create the custom IP, I add the .v file of the top module that uses dds compilers. However I see their definitions are not updated in the Sources tab. There is another component the top module refers, which when added to the project, got updated.

 

Can you help me how I can have the top module refer to DDS compilers, before proceeding to packaging the IP?

 

Thanks in advance,

 

 

-Chandrasekhar DVS

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Registered: ‎11-09-2015

HI @krishnachandrasekhar100 

I do not have the project files so I am not sure what you are talking about.

I would suggest you create a new topic and see if anybody from the community can help.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎05-22-2018

Ok sure, I will do that.

 

-Chandrasekhar DVS

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