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Registered: ‎09-04-2019

Choosing JESD line rate and clocking


Could somebody pls acknowledge/comment on my understanding and configurations of JESD204B subclass 1. Below are the configurations :

1. DAC FS = 8847.36 MSPS with DUC inp. factor = 18x with input data rate of 491.52 MSPS.

2. ADC FS = 2949.12 MSPS with DDC dec. factor = 6x giving out data @ the rate of 491.52 MSPS.

According to datasheet, Input reference clock to RF  = 368.64 MHz (on-chip PLL/VCO circuit has x24 factor which makes upto 8847.36 MHz) and clock for the ADC is generated by dividing the integrated PLL and VCO output by 3 = 2949.12 MHz )

Same refclk of 368.64 MHz is also given to fpga jesdphy QPLL from LMK, Sysref frequency is 15.36MHz on both sides.

I want to use it for LMFS - 4421 for 2TX mode, where I calculated line rate using formula, FC - 368.64M,N-16,S-1

(M x S x N’ x 10/8 x FC) / L = 7.3728 Gbps/lane. From table 6-52, M is chosen as 4 ( 2 IQ pairs for 2 Dacs)

M as per datasheet - Number of I or Q streams per device (2 = 1 IQ pair, 4 = 2 IQ pairs, 8 = 4 IQ pairs).

I have a design of independent JESD cores for RX and TX with 4 lanes sharing a common JESDPHY of 4 lanes with QPLL being used. JESD Core clk = data rate/40 = 184.32 MHz,  DRP and AXI clock taken care with valid ranges.

Transceiver datasheet snaps of limitations and JESD frame format are attached below.

Could somebody tell, the calculations mentioned above and clocking schemes are correct..?


Thanks in advance.

2 Replies
Registered: ‎05-22-2018

Hi rakssss,


I too am looking into similar stuff. Can you tell me what N ans S parameters are and why did you take them to be 16 and 1? 

Also could you point the document you are referring to?


I too would like to know if raksssss's calculation is correct. If anyone could verify, that would be great!


Thanks in advance,



-Chandrasekhar DVS

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Registered: ‎09-04-2019

Hi @krishnachandrasekhar100,

N is the number of bits which usually referred as DAC resolution. If dac resolution is 14 bit, N = dac bits + tail bits which makes up 16 bit I/Q sample. You can go through the following links for better understanding.

Even I am not sure and not understood better about S which is defined as number of samples/frame, mostly I see this parameter set as 1.

One correction in above params I feel is FC is set according to input data rate of DAC, not wrt devclk/refclk, my case is 491.52 MSPS which would give lane rate of 9.3 Gbps.

Here are some of the links which I frequently go through while working on JESD.,122,284

Also, can refer to the official JEDEC JESD guide from their website.

Thanks and regards,