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Erin
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Registered: ‎07-23-2020

Clk Wiz 3.6 (ISE) to Clk Wiz 6.0 (Vivado)

Migrating from Spartan 6 to Spartan 7, I need to generate new cores. I was able to successfully reverse-engineer the two FIFO_Generator IP Cores from ISE and then subsequently re-create them in Vivado, but I am having difficulty with the transition of the CLK_Wiz Core. 

Attached are the corresponding screenshots from ISE (old) and Vivado (new), specifically referring to the areas I am struggling to find correspondence with.

In regards to the output clock, in ISE, I was able to specify one of the output clocks to have a frequency as low as 1 MHz, which is what was specified in an inherited core, but in Vivado, it throws up an error when I try to input a 1 MHz frequency for the second clk_out.

The Override Mode from ISE does not seem to correlate cleanly to the Override Mode for Vivado. In the screenshot for ISE, I have everything set up the way it is needed. Could you throw in a screenshot, or explain how to get those specifications for the new Vivado core generation?

Vivado_CLK_WIZ_6_0_Override_Mode_1.PNG
Vivado_CLK_WIZ_6_0_Override_Mode_2.PNG
ISE_CLK_WIZ_3_6_Output_Clock.PNG
Vivado_CLK_WIZ_6_0_Output_Clock.PNG
ISE_CLK_WIZ_3_6_Override_Mode.PNG
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Registered: ‎01-22-2015

@Erin 

The problem is that outputs of the MMCM usually have a minimum frequency of 4.69 MHz (see MMCM_FOUTMIN in Table 37 of datasheet, DS189).

There is a special setup for the MMCM called CLKOUT4_CASCADE that allows you to get one output as low as 0.036MHz.  However, to get a 1MHz clock, I think you will find it easier to specify one output the MMCM to be 8.0MHz. On this 8.0MHz output, place a BUFR that is configured to divide the clock frequency by 8. 

Pages 288-290 of UG953 show you how to instantiate the BUFR into your Vivado project. 

Finally, manually adjusting things under the "Settings" tab of the Vivado Clocking Wizard is seldom necessary and often leads to problems.

Cheers,
Mark

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Erin
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Registered: ‎07-23-2020

Thank You, that helps. Just to clarify, am I able to instantiate the BUFR within the clk wiz IP core generator within Vivado? Or do I need to create the clk wiz without the BUFR and then edit the .xci file that is created?
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Registered: ‎01-22-2015

The Clocking Wizard allows you to select different buffers for each of the MMCM clock outputs.  Oddly, BUFR is not a option.  So, in the Clocking Wizard, you will need to select "No buffer" for the 8MHz clock output.  Then, manually instantiate the BUFR in your project and connect it to the 8MHz clock output of the MMCM.

clk_wiz_no_buffer.jpg

In your project, do you directly cross (ie. no synchronizer) data from the 1MHz clock-domain to other clock domains?

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Erin
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Registered: ‎07-23-2020

I am migrating inherited cores over, and I am not overly familiar with FPGAs. I do not believe that a synchronizer is used, but where do I go to check that?

Also, I noticed in UG953 that you mentioned to look at, there is the specific verilog instantiation of the BUFR, but do I include that in the created .xci file? Or do I create a new file? I am not sure where to put the instantiation.

I was also speaking with my team lead, and he mentioned the possibility of being able to run the clock at 8MHz without the divide/buffer. Do you have any guidance for where to look/ how to determine the necessity of the bufr in this case?

Vivado_BUFR_Instantiation.PNG
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Registered: ‎01-22-2015

I am migrating inherited cores over, and I am not overly familiar with FPGAs. I do not believe that a synchronizer is used, but where do I go to check that?

No worries.  We can postpone answering this question until you run Vivado implementation and timing analysis.

 

Also, I noticed in UG953 that you mentioned to look at, there is the specific verilog instantiation of the BUFR, but do I include that in the created .xci file? Or do I create a new file?

Inside the same verilog file where you instantiate the MMCM, you can also instantiate the BUFR.

 

...the possibility of being able to run the clock at 8MHz without the divide/buffer. Do you have any guidance for where to look/ how to determine the necessity of the bufr in this case?

In this case, forget about the BUFR for now.  In the Clocking Wizard, don't use "No buffer" on the 8MHz output of the MMCM.  Instead, use the default BUFG buffer.  Later, when you run Vivado implementation and timing analysis, we should learn whether 8MHz (instead of 1MHz) is ok.

 

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