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swjtumaxiaobao
Observer
Observer
481 Views
Registered: ‎06-04-2019

Clock wizzard VS my Clock division circuit

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Hello, I'm confused about the Clock wizaard IP and Clock division circuit using counter to just generate a divider clock signal. Could you tell me the difference between them or just let me know how does the IP implement and in which situation should I use the IP instead of writing a counter by myself. I found an expression in https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/Spartan-6-clocking-wizzard-ip-or-quot-manually-quot-derive-a/m-p/139462#M10600  but I'm still not clear about the difference. 

Thanks a lot!

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drjohnsmith
Teacher
Teacher
433 Views
Registered: ‎07-09-2009

draw a picture of your counter circuit,

    and the timing diagram. 

you will see that the clock you generate is always going to be delayed compared to the clock coming in,

   A delay is un desirable if you want to run at anything apart from slow speeds, and if you do , will pribably require a cros sdomain clock circuit , as the input clock and the clock you generate have an un defined phas erelatiosn ship.

 

also , 

   the clock circuit in a FPGA uses clock routing, whilst as your logic circuit will use the internal logic routes. The clock routes are few, but are designed for very fast, low phase delay clock transmission across the chip, whilst logic nets are everywhere, but have a a much greater delay. And moving form one network to the other adds another delay.

So generally, use the clock wizard to generate clocks.

 

Also , if you have say a 200 MHz clock generated, and want some logic to run at 100 Hz

     then feed the logic with 200 MHz clock, and enable the logic on alternate clocks, 

      this makes your clock management easier, 

 

So in general,

   use the clock wizard for you main clocks

      use logic with enable for integer divisions of the main clocks

   

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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4 Replies
bruce_karaffa
Scholar
Scholar
447 Views
Registered: ‎06-21-2017

@swjtumaxiaobao  If the new clock is in the frequency range that can be implemented using the clock wizard, use the clock wizard.  This will give you a fixed phase relationship between the original clock and any clocks generated by the wizard.  The wizard will instantiate the necessary clock buggers and keep all of your clock signals on the low skew clock routing trees.  If you use a clock divider, it will be implemented in regular FPGA fabric and the timing will change every time you build.  If the desired new clock frequency is lower than you can reach with the clock wizard, usually the best thing is to use a counter to generate a clock enable as opposed to a clock.  This way you will get more consistent timing and avoid a clock domain crossing. 

drjohnsmith
Teacher
Teacher
434 Views
Registered: ‎07-09-2009

draw a picture of your counter circuit,

    and the timing diagram. 

you will see that the clock you generate is always going to be delayed compared to the clock coming in,

   A delay is un desirable if you want to run at anything apart from slow speeds, and if you do , will pribably require a cros sdomain clock circuit , as the input clock and the clock you generate have an un defined phas erelatiosn ship.

 

also , 

   the clock circuit in a FPGA uses clock routing, whilst as your logic circuit will use the internal logic routes. The clock routes are few, but are designed for very fast, low phase delay clock transmission across the chip, whilst logic nets are everywhere, but have a a much greater delay. And moving form one network to the other adds another delay.

So generally, use the clock wizard to generate clocks.

 

Also , if you have say a 200 MHz clock generated, and want some logic to run at 100 Hz

     then feed the logic with 200 MHz clock, and enable the logic on alternate clocks, 

      this makes your clock management easier, 

 

So in general,

   use the clock wizard for you main clocks

      use logic with enable for integer divisions of the main clocks

   

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

swjtumaxiaobao
Observer
Observer
404 Views
Registered: ‎06-04-2019

Very happy to get your help and learned a lot of new things. I appreciate your help deeply. Thanks for letting me know so much things. What you say lets me realize the importance of FPGA resources and the physical layout and implementation behind them. I will continue to learn more about this field. Thanks so much!

swjtumaxiaobao
Observer
Observer
400 Views
Registered: ‎06-04-2019

Very happy to get your help and learned a lot of new things. I appreciate your help deeply. Thanks for letting me know so much things. What you say lets me realize the importance of FPGA resources and the physical layout and implementation behind them. I will continue to learn more about this field. Thanks so much! Thanks for both for your help!!!

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