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zan_zhan@amat.com
Adventurer
Adventurer
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Registered: ‎01-24-2018

Common Clock Built-in FIFO SRST in Virtex Ultra Plus FPGA.

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Hi Everyone,

I have bunch of Common Clock Built-in FIFO in my design of Virtex Ultra Plus FPGA. 

My question is About how to correctly handle SRST of Common Clock Built-in FIFO.

Assuming clock is always stable and SRST is synchronous reset,

Is it ok or safe to apply 1 clock cycle high pulse on SRST to reset FIFO?

If not, what is the correct way to reset FIFO?

 

Thanks a lot.

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pthakare
Moderator
Moderator
288 Views
Registered: ‎08-08-2017

Hi zan_zhan@amat.com 

Atleast one clock cycle is okay .

for your reference please check the RESET section in PG057  -> page 136

https://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v13_2/pg057-fifo-generator.pdf

 

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1 Reply
pthakare
Moderator
Moderator
289 Views
Registered: ‎08-08-2017

Hi zan_zhan@amat.com 

Atleast one clock cycle is okay .

for your reference please check the RESET section in PG057  -> page 136

https://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v13_2/pg057-fifo-generator.pdf

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post