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gszakacs
Instructor
Instructor
10,132 Views
Registered: ‎08-14-2007

CoreGen FIFO Generator v6.1 - Behavioral model does not assert prog_empty flag

I looked in the known issues for FIFO Generator v6.1 and did not see this issue described

(http://www.xilinx.com/support/answers/35524.htm)

 

I generated a 40-wide, 32 deep dual clock distributed RAM FIFO for Spartan 6.  It has

a programmable empty assert threshold of 8.  When built with the behavioral model

the simulation shows prog_empty de-asserted after the first write, in fact one cycle

before the empty flag de-asserts, and then never re-asserted.

 

The structural model seems to show the proper behavior for the flag.

 

Also in the process of changing the core to provide a stuctural model, I found

that the default double-click action on existing IP within the CoreGen GUI is

to re-customize the core under the original project settings, not the current

settings which I had just changed.  This cost me an extra generation and

simulation cycle before I found out that the model had not changed.  In

the previous versions of CoreGen, the actions for an existing IP showed up

in the main window.  In 12.1, the actions have been pushed down the page

to where you need to scroll down to find them.  This is why I tried to re-customize

by double-clicking the IP.  After finding that a right-click on the IP offered the

options I needed (and also highlighted the default action so I saw where

the previous generation went wrong), I also found the actions in the main

window.

 

Regards,

Gabor

-- Gabor
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matttay
Observer
Observer
10,124 Views
Registered: ‎01-13-2010

Hi, I've also just encountered a prog_empty issue with FIFO generator in ISE 12 for spartan sc3s400 256

 

I just deleted an older FIFO that was working as expected so that I could use the new memory generator. I set it the same as the previous fifo, with separate clocks. The FIFO is 32 wide, 64 deep. The prog empty thresh was set to to 32. Fall through enabled. 

 

In sim, the prog_empty starts asserted (expected). After 6 writes to the fifo it goes low (unexpected). I changed thresh to 62. Same behavior. The write clock is about 10% slower than the read clock. But no reads have been done yet.

 

Cleaned project files, tried again. Same.

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gszakacs
Instructor
Instructor
10,115 Views
Registered: ‎08-14-2007

It sounds like the same bug.  My FIFO was also first word fall-through.  I would suggest

changing the Coregen project options to generate a structional simulation model.  At least

in my case the structural model worked as expected.

 

Regards,

Gabor

-- Gabor
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