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Registered: ‎08-04-2009

Coregen - FIFO reg



I have generated the FIFO with the following setting


CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=fifo_generator_v4_4

CSET data_count=true
CSET data_count_width=10
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET fifo_implementation=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=1022
CSET full_threshold_negate_value=1021
CSET input_data_width=27
CSET input_depth=1024
CSET output_data_width=27
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=true
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
# END Parameters


FIFO works fine when fifo_rd_en and fifo_wr_en are given with the same signal....


The data in to FIFO is at a slower rate when compared to FIFO_clk  and data_out is read at FIFO_clk 

For this ,

1) I have given the wr_en with a slower clk , even though FIFO clk is higher ...

2) I have checked the if  data_count is greater than 500 and then rd_en is made high

3) After reading 256 datas I have made rd_en=0


While the fifo_rd_en = high , I find the values read from the fifo ,

0- 1A = remains 00000000

1B- 39 = some values(hopefully from fifo)

above 40 to 255 = remains zero....


Why does this happen ? Any reasons?





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1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎04-06-2010

I have several questions for you:


1. Are you experiencing this in simulation or hardware?

2. Have you tried your same test with a newer version of the core; ie v6.1

3. Why are you using a common clock BRAM configuration if you're using two different clocks for your read and write data?



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