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Visitor
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Registered: ‎05-28-2020

Custom IP with master AXI Lite

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Hi all,

 

I want to design an IP which has a BRAM with a true dual port.

1. Port A is connected via a Slave AXI Lite connected to the PS. A Linux running on the PS writes an array of 1024x32 bit into the BRAM.

2. Port B "should" be connected to a Pmod digital-to-analog DA3 and outputs each row of the 1024 values.

I have a question here, I think Xilinx Axi Master Lite is deprecated for some reason or another! I don't know why! So I have to use a AXI Full interface for the master side. Is it a correct solution to take? Sending each row of 1024x32 bits one by one on each clock to the AXI Full Master interface (it is not easy for me though).

I just want to put the ARM processing system aside and just stay to the FPGA part.  How can have a master interface on my custom IP? beside, the story I told makes sense or do you suggest a better solution?

 

Any comment is highly appreciated

Best

Jan

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Scholar
Scholar
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Registered: ‎05-21-2015

@janoliver ,

You mean ... you want to drive an outgoing SPI-based DAC using a flash memory controller?  Wouldn't it make more sense to build an SPI controller of your own to drive the DAC?

always @(posedge S_AXI_ACLK)
if (TVALID && TREADY)
begin
    tready_sreg <= { 32'h0 };
    mosi_sreg <= { {(2){S_AXIS_TDATA[15]}, {(2){S_AXIS_TDATA[14]}, {(2){S_AXIS_TDATA[13]}, // .... };
    sclk_sreg <= 32'h5555_5555;
    S_AXIS_TREADY <= 0;
    CS_N <= 1'b1;
    SCLK <= 1'b1;
end else begin
    tready_sreg <= { tready_sreg[30:0], 1'b1 };
    S_AXIS_TREADY <= tready_sreg[31];
    sclk_sreg <= { sclk_sreg[30:0], 1'b1 };
    SCLK <= sclk_sreg[31];
    CS_N <= (&sclk_sreg[30:0]);
end

SPI control is really nothing more than a bunch of shift registers.  It'd be a whole lot easier to do that than to try to create an AXI master when none was needed.

Dan

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Scholar
Scholar
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Registered: ‎05-21-2015

@janoliver ,

I'm not sure I follow ... you want to build an AXI slave that can be used to read and write a wave table from which you will drive a DAC.  You want to control this AXI slave from the PS.  That much makes sense so far.

So ... why do you need a second AXI master?  To drive this slave?  Why not just drive it from the PS?  Do you want to drive the second port of this slave?  The one that would read the outputs back out?  If so, why?  AXI like any other bus structure is known for unpredictable delays which get in the way of signal generation.  Why not skip the AXI entirely on the second port and thus actually get the performance you are looking for?

Dan

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Voyager
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Registered: ‎05-11-2015

 

Deprecated? No, I don't think so. AxiLite is really useful because you don't always want the full fledge.

It may have confused you that the PS ports are "AXI", but you can connect them (through interconnects) to AxiLite ports.

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Visitor
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Registered: ‎05-28-2020

Hi @dgisselq 

Thanks for your reply. The block diagram looks something like this:

Screenshot from 2020-10-08 18-21-31.png

I wanted to make the waveform generation independent of the PS part (and I don't know how to drive the pmod from the Linux I have on PS).

So, inside my custom waveform generator is actually a BRAM storing the signal samples, from the slave side, and then fed to the Pmod from the Master side.

What do you suggest?

 

Regards,

Jan

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Registered: ‎05-28-2020

Hi @joancab 

 

I was mentioning from this link: https://www.xilinx.com/support/answers/62549.html

"The two AXI IPIF helper IPs (axi_master_lite_v3_0 and axi_slave_burst_v2_0) along with proc_common_v4_0 have been removed from the 2014.3 Vivado installation directory."

I wanted to use AXI Master Lite IPIF. If not IPIF, how can one connect a BRAM read port to the AXI Master to be written to the other slave?

Any suggestion?

 

Regards,

Jan

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Scholar
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Registered: ‎05-21-2015

@janoliver ,

I spent some time digging into Xilinx's IPIF implementation.  It's not worth resurrecting.  Better (and simpler) AXI-lite implementations exist.

You can use that demo design (don't use Xilinx's--it's broken) to write to a table using RTL.  You can then read from that table using an incrementing address.  From there you can feed the DAC and be okay.

Bottom line: This is easy to do in RTL.  If you try to block design all the components, you'll find that lots of things come close to fitting, but few do exactly the job you need.

Dan

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Visitor
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Registered: ‎05-28-2020

Dear Dan,

Thanks for your time to answer me. I took a look at your website and your talk. Kudos to you.

The link you provide me (easyaxil.v) points to the AXI-Lite slave interface. Do you have code for master interface as well? I mean to "feed the DAC" as you said or am I missing something?

I also prefer RTL but I just wanted to show you a schematic of my design.

 

Regards,

Jan

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Scholar
Scholar
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Registered: ‎05-21-2015

@janoliver ,

Yes, I have AXI master examples.  The simplest is this bridge from Wishbone to AXI, more complex examples are also discussed on the blog under the heading, "The Hard part of building a bursting AXI master."

I would not recommend using the AXI memory mapped protocol (sometimes called AXI full) for streaming data, nor would I recommend AXI-lite.  So while I have examples of how the AXI protocol can be used for that purpose (linked above), the protocol is ill suited for a such a purpose.  AXI stream is a much better protocol for moving sampled data around.

If I understand your problem well, you want an AXI-lite slave interface and an AXI stream master interface.  The AXI-lite slave interface will generate a table, that will then be used to generate a periodic signal of some type, right?  Something like ...

// EasyAXIL slave interface
always @(posedge S_AXI_ACLK)
if (axil_write_ready)
    table[awskd_addr] <= wskd_data;

always @(posedge S_AXI_ACLK)
if (!S_AXI_RVALID || S_AXI_RREADY)
    S_AXI_RDATA <= table[arskd_addr];

// Now for the outgoing AXI stream
// You'll need to determine when to send new data out--typically on
// a regular schedule, such as every N'th clock
//
// always @(posedge S_AXI_ACLK)
//   time_for_new_data <= something;
//
always @(posedge S_AXI_ACLK)
if (!S_AXIS_ARESETN)
    M_AXIS_TVALID <= 0;
else if (!M_AXIS_TVALID || M_AXIS_TREADY)
    M_AXIS_TVALID <= (time_for_new_data); // You need to decide on this signal

// Increment the table address
always @(posedge S_AXI_ACLK)
if (time_for_new_data)
    { dds_address, sub_address } <= { dds_address, sub_address } + frequency_step;

// Read new data when it's time to do so
// But ... in case the AXI stream is stalled, don't violate protocol.
// This leads to repeated words--not a good thing, so don't stall the
// AXI stream bus.
always @(posedge S_AXI_ACLK)
if ((!M_AXIS_TVALID || M_AXIS_TREADY)&&(time_for_new_data))
    M_AXIS_TDATA <= table[dds_address];

// The definition M_AXIS_TLAST, if used at all, would be application dependent

This sort of application doesn't need an AXI master--unless I've misunderstood what it is you are trying to develop.

Incidentally, for more information on this type of design, check out lesson three of my (still work in progress) intermediate tutorial.  I discuss there how to build something like this.  Lesson two discusses AXI-lite.  (I'd provide more links, but I've been told that posts with more than two links will be flagged as spam and removed from this system.)

Dan

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Registered: ‎05-28-2020

Dear Dan,

I have a Pmod DA3 which is a digital-to-analog convertor. The IPs needed to drive this Pmod consists of a Quad SPI IP connected to a Pmod Bridge to a Pmod interface. Quad SPI only supports AXI-Lite and AXI4-Full so AXI-Stream (which I like the most) is not an option here... This is the constraint that I have to unfortunately deal with.

 

As I explained early in my intro post, I have a custom IP which reads a BRAM and should move the data from Port B of the BRAM to the Pmod. So I am looking for a solution to connect BRAM Port B to AXI-Lite (or AXI4-Full).  Could you please tell me if the design decision I have made is totally wrong or what do you mean by this sort of application doesn't need an AXI master?

I am at the moment, taking a look at your comment from another post here: https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Native-Control-of-AXI4-Lite-Master/m-p/978697/highlight/true#M48201

And also the great Tutorial on your website that you have already mentioned:  https://zipcpu.com/tutorial/

 

Best regards,

Jan

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Scholar
Scholar
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Registered: ‎05-21-2015

@janoliver ,

You mean ... you want to drive an outgoing SPI-based DAC using a flash memory controller?  Wouldn't it make more sense to build an SPI controller of your own to drive the DAC?

always @(posedge S_AXI_ACLK)
if (TVALID && TREADY)
begin
    tready_sreg <= { 32'h0 };
    mosi_sreg <= { {(2){S_AXIS_TDATA[15]}, {(2){S_AXIS_TDATA[14]}, {(2){S_AXIS_TDATA[13]}, // .... };
    sclk_sreg <= 32'h5555_5555;
    S_AXIS_TREADY <= 0;
    CS_N <= 1'b1;
    SCLK <= 1'b1;
end else begin
    tready_sreg <= { tready_sreg[30:0], 1'b1 };
    S_AXIS_TREADY <= tready_sreg[31];
    sclk_sreg <= { sclk_sreg[30:0], 1'b1 };
    SCLK <= sclk_sreg[31];
    CS_N <= (&sclk_sreg[30:0]);
end

SPI control is really nothing more than a bunch of shift registers.  It'd be a whole lot easier to do that than to try to create an AXI master when none was needed.

Dan

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Registered: ‎05-28-2020
Dear @dgisselq,

As you said, I found that just adding a simple FSM would solve my problem of connecting to Pmod. AXI was really an overkill. Thanks for your advice.