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Adventurer
Adventurer
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Registered: ‎09-28-2020

DDR MIG IP

Hi,

pg 150 MIG Chapter 4 tells this  

The address read/address write modules are responsible for chopping the AXI4 incr/wrap
requests into smaller memory size burst lengths of either four or eight, and also conveying
the smaller burst lengths to the read/write data modules so they can interact with the user
interface .

This statement  telling if AXI User Interface is supporting a burst length of 256 , will this modules further break this 256 (axlen = o-255) , as AXI4 supports odd number burst length , if yes how will it break  for odd or even burst length.

Please do reply ,

Thanks in advance.

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11 Replies
dgisselq
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Scholar
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Registered: ‎05-21-2015

@Learn ,

I would be surprised if the design broke at all.

As for burst to burst mapping, we've discussed that quite a bit here.  You are still missing the reality that the AXI bus width is not the same as the DDR width, and so the two bursts are not compatible or comparable.  If the MIG controller is set at 4:1, and the DDR width is 8-bits, then for an AXI bus of a 64-bit width each AXI beat will map to a single 8-byte DDR bursts.  Hence, a 256 beat AXI burst (AxLEN=8'hff) would map to 256 DDR bursts each of length 8.  If the AXI bus is smaller, you'd still get the same number of DDR bursts--they'd just be filled with a smaller amount of information--the data mask bits would be used to make certain that data bits are properly broken down during writes and extra read bits would be ignored.  If the AXI bus were larger, it would then take you two or more DDR bursts for each AXI beat.

Try thinking about this in terms of clock cycles, rather than DDR burst lengths.  When mapped at 4:1, a common DDR mapping, one AXI clock period maps to an entire DDR burst of 8-bytes.  (Assuming the DDR has 8-data bits, it would be 16 bytes for 16 data bits, etc.)  AXI can only send one beat of information per clock period.  Therefore, an AXI burst of AxLEN will require (AxLEN+1) clock periods at a minimum independent of how the DDR is set up.

Dan

Learn
Adventurer
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518 Views
Registered: ‎09-28-2020

Hi Dan,

Thanks for the reply

 

I agreed with previous reply , please do check this

This is not related to the xilinx ip

when designing the ip we need to decide on the controller clock ratio

suppose let us consider the ddr data bus is 16 bit wide, ddr Burst len is 16 .

1. Axi data width is 64 bit , what should be the MIG controller clock ratio

   I think the clock ratio as to be 2:1 , as ddr can get in 2 clock cycles a 64 bit  [at posedge 16 & negedge 16 bit data] so ddr operates 2 times faster than controller .

2. Axi data width is 32 bit , what should be the MIG controller clock ratio

   I think the clock ratio as to be 1:1 , as ddr can get in 1 clock cycle a 32 bit[at posedge 16 & negedge 16 bit data] so ddr operates as same as controller .

is this correct here we need to decide on the clock ratio of MIG.

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dgisselq
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Registered: ‎05-21-2015

@Learn ,

I think you'll find that the clock ratio is constrained by timing within the FPGA, rather than by the (unrestricted) designer's choice.

Dan

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Learn
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Registered: ‎09-28-2020

Hi Dan,

Thanks for the reply

If we are designing the IP Controller and we need to decide the Controller clock ratio for our requirement  in that case how can we decide  ,

is my understanding correct

when designing the ip we need to decide on the controller clock ratio

suppose let us consider the ddr data bus is 16 bit wide, ddr Burst len is 16 .

1. Axi data width is 64 bit , what should be the MIG controller clock ratio

   I think the clock ratio as to be 2:1 , as ddr can get in 2 clock cycles a 64 bit  [at posedge 16 & negedge 16 bit data] so ddr operates 2 times faster than controller .

2. Axi data width is 32 bit , what should be the MIG controller clock ratio

   I think the clock ratio as to be 1:1 , as ddr can get in 1 clock cycle a 32 bit[at posedge 16 & negedge 16 bit data] so ddr operates as same as controller .

is this correct here we need to decide on the clock ratio of MIG.

 

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@Learn ,

It's not that simple.  You need to actually build a working controller, and that depends upon meeting timing requirements within your design.  In general, I can't get my designs to close at the speeds that would be required of a 2:1 clock ratio, but 4:1 is quite reasonable.  This is based upon more than just the DDR controller, but also the speed of the rest of the design that is necessary to interact with it.  Do you want to run your FPGA designs at 200MHz+?  If not, you might want to drop back to a 4:1 ratio.

Dan

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Learn
Adventurer
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Registered: ‎09-28-2020

Hi Dan, Thanks for the reply.  

We are actually designing the IP completely in other FPGA platform and we are using xilinx MIG IP as the reference to understand the concepts.

The requirement is to decide on this clock ratio the DDR data is 16 bit, DDR burst is 16  and user axi interface is 32 bit and 64 bit .

If we are designing the IP Controller and we need to decide the Controller clock ratio for our requirement  in that case how can we decide  ,

is my understanding correct

when designing the ip we need to decide on the controller clock ratio

suppose let us consider the ddr data bus is 16 bit wide, ddr Burst len is 16 .

1. Axi data width is 64 bit , what should be the MIG controller clock ratio

   I think the clock ratio as to be 2:1 , as ddr can get in 2 clock cycles a 64 bit  [at posedge 16 & negedge 16 bit data] so ddr operates 2 times faster than controller .

2. Axi data width is 32 bit , what should be the MIG controller clock ratio

   I think the clock ratio as to be 1:1 , as ddr can get in 1 clock cycle a 32 bit[at posedge 16 & negedge 16 bit data] so ddr operates as same as controller .

is this correct here we need to decide on the clock ratio of MIG.

 

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dgisselq
Scholar
Scholar
440 Views
Registered: ‎05-21-2015

@Learn ,

The MIG controller to clock ratio is not impacted by the width of either the AXI bus or the DDR controller.  The driving engineering constraint when selecting this clock ratio is design timing.  While design timing includes the timing within the DDR controller, it also includes timing considerations throughout the rest of the design.

You will also find that scheduling DDR requests becomes much easier with a 4:1 clock ratio ... but that's further along in your project than you are at right now.

If this is really what you want to do, then you might wish to check out this project--which came pretty close to what you are hoping to do.  Sure, you would need to put an AXI to Wishbone bridge on the front end of it, but such a bridge already exists.

Dan

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Learn
Adventurer
Adventurer
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Registered: ‎09-28-2020

Hi Dan,

Thanks for the reply .   

Please consider this as general one not related to xilinx IP.

We have a DDR data width is 16 bit,and our user axi interface datawidth is 64 bit so for 2 clock cycle from DDR we will get a 64 bit data that data controller takes and presents to axi interface of 64 bit, so we could say DDR is operating 2 the clock rate of what other logic is operating if iam wrong please tell me how is MIG controller clock ratio decided.

 

 

 

 

 

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dgisselq
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Scholar
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Registered: ‎05-21-2015

@Learn ,

Do me a favor ... if this is not about Xilinx IP, then let's stop using the term "MIG".  The MIG core is generated by Xilinx's Memory Interface Generator.  If you are building a generic DDR3 controller, then the MIG is really irrelevant unless you wish to study how it works.

Let me ask you this: What clock rate are you targeting the rest of your logic to be running at?  Because that's a key to this whole thing, and not all clock rates are even possible.  That will also drive your subclocking ratio.

Dan

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Learn
Adventurer
Adventurer
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Registered: ‎09-28-2020

Hi Dan, Thanks for the reply. 

We are targeting our design to run at 100MHz (axi interface  data bus width is 64 bit) so DDR will be running at 200MHZ( DQ is 16 bit, for 2 cycles we get 64bit data).

 

 

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dgisselq
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Scholar
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Registered: ‎05-21-2015

@Learn ,

Not so fast.  Many DDR SDRAMs have both minimum and maximum clock speeds associated with their interface.  Which DDR standard are you working with?  DDR, DDR2, DDR3, LPDDR4?  Which memory speed chip?

Dan

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