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chrisdekoh
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Registered: ‎06-02-2008

DDR2 on virtex 5 FPGA

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Hi,

   I am trying to get MIG's DDR2 controller to work. I have some questions with regards to this. I am referring to documents xapp858 and and the user guide which is generated everytime a new DDR2 controller is generated. The user guide (in section IV: virtex-5 FPGA to Memory Interfaces) states that if i were to use the controller which has a dcm with no testbench, the clock supplied must be

1) a differential input 200 MHz clk, clk200_p and clk200_n

2) a differential input sys_clk_p and sys_clk_n, (for me, I need it to run at 133 MHz)

 

what is the recommended way to generate the above 2 clocks. The clock into the system is a master clock runing at 100 MHz.

 

I thought of feeding input clock into DCM to multiply it to 400 MHz (x3). Next i will step it down using another DCM (divide by 3) to 133 MHz.

the 200 MHz clock will be generated by using DCM with input clock and multiply to 200 MHz.

 

1) is this way of generation correct? I am afraid of scenario having too many DCM having undesirable effects

2) if this way of generation is wrong, then how should i do it? does xilinx have any recommended way on how this should be done?

3) how do you generate the differential clock using the single ended output clocks from the DCM?

 

P.S. I am using MIG 2.1

thanks!

Chris

 

 

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barryabrown
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Registered: ‎09-11-2007

You don't need to generate differential clocks.  All of the clock and reset stuff is in the file <design>_infrastructure.vhd, and you can replace it with your own design, then modify the top file that instantiates that one.  My design uses a single clock input and a Virtex5 PLL to generate all of the frequencies needed.

 

Barry

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barryabrown
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Registered: ‎09-11-2007

You don't need to generate differential clocks.  All of the clock and reset stuff is in the file <design>_infrastructure.vhd, and you can replace it with your own design, then modify the top file that instantiates that one.  My design uses a single clock input and a Virtex5 PLL to generate all of the frequencies needed.

 

Barry

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chrisdekoh
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Registered: ‎06-02-2008
Hi,
 
this is what i have done.
 
1) modify the infrastructure block such that the clocks do not go into through the differential buffers.
2) use one DCM to generate the 133 MHz clock and 200 MHz clock
3) write a testbench and run the simulation on this modified setup.
 
the phy_init_done never seems to lock. any idea why? I measured the generated 133 MHz clock in the simulator, the clock period is 7500 ps whereas the one defined in the ddr2 controller file is 7518 ps. Even when i modified it to 7500 ps, it fails to work. any idea?
 
Chris
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barryabrown
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Registered: ‎09-11-2007

Are you waiting long enough?  If generic SIM_ONLY = '0', my 266MHz design takes about 300 usec before phy_init_done is true.  For simulation only, you can set SIM_ONLY = '1' and it will be much faster (about 40 usec). 

 

 

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barryabrown
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Registered: ‎09-11-2007
I notice you are using MIG 2.1 (I used 2.0).  Does it also need a signal clkdiv0 at 133/2 MHz?
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blocur
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Registered: ‎10-22-2008

Hi, im using Virtex 5 pci express board, and MIG 2.1 for ddr2 controller.

 

My question is if i can use clock synthesisers (U6 & U17) for sys_clk_p/n and clk200_p/n.

I've set them for 100MHz (system clock) and 200MHz (ddr2 clock) but during mapping process i get this error :

 

Pack:1107 - Unable to combine the following symbols into a single IOB component: PAD symbol "clk200_n" (Pad Signal = clk200_n) SlaveBuffer symbol "u_infrastructure/u_ibufg_clk200/SLAVEBUF.DIFFIN" (Output Signal = u_infrastructure/u_ibufg_clk200/SLAVEBUF.DIFFIN) An IO component of type IOB was chosen because the IO contains symbols and/or properties consistent with input, output, or bi-directional usage and contains no other symbols or properties that require a more specific IO component type. Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "clk200_n" (LOC=C8 [Physical Site Type = IPAD]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly.

 

Is this error and clock source i've used connected, or the reason of error is somewhere else? 

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