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Roja
Newbie
Newbie
294 Views
Registered: ‎03-03-2021

DDS Compiler 4.0 in Xilinx ISE 13.4

Hi

We are using DDS Compiler 4.0, In that we are generating 10MHZ output frequency by giving system clock 100 MHZ. 

10 samples it will take to create sinewave. samples are getting from DDS compiler is signed or unsigned.

We required unsigned samples to construct a sinewave, because we are using DAC which it will take only positive values to reconstuct the sinewave, please let us know, is there any parameter in the IP to give unsigned samples to reconstruct sinewave.

 

Thanks

Roja V

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3 Replies
bruce_karaffa
Scholar
Scholar
289 Views
Registered: ‎06-21-2017

You could try inverting the most significant bit of the DDS output.

Roja
Newbie
Newbie
288 Views
Registered: ‎03-03-2021

If i try Most significant bit, some unsigned value will change right.

Is there any option in IP to get output will be unsigned.

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drjohnsmith
Teacher
Teacher
248 Views
Registered: ‎07-09-2009

are you certain your DAC can not accept different input formats ?

Also, why you using such an ancient version of ISE, 

    what OS are you running that on ?

What you are looking for is to convert from signed ( 2s compliment )  to offset binary

 

If you look at say 6 and -6

 

real    binary     2's comp

6        1110        0110

-6       0010       1010

 

To convert, invert the top bit.

works in range 2**n-1 to - 2**n-1 -1

 

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