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Visitor
Visitor
8,578 Views
Registered: ‎04-02-2015

Data width and deep limitation in block ram(Spartan6)

Hello

I am analysing a reference design(attachment) .

that design have some True Dual Port BRAM(32bit wide and 2048 deep used as circular line buffers) generated using Block Memory Generator, version 6.3, in Xilinx CORE Generator with Atlys(spartan6 , FPGA part: xc6slx45-csg325) board.

 

but I reduced a fact that bram maximum size is 18kb from  Spartan-6 FPGA Block RAM ResourcesUser Guide(attachment).

 

18kb ( memory depth and data width : 512*32 , 1024*16 , 2048 * 8) table 4 , Block RAM Data Combinations

 

I think that set( 32bit wide and 2048 deep = 64kb) exceed maximum memory size(18kb).

 

I wonder that whether that bram set(32bit , 2048 deep) is correct or not.

 

 

 

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Xilinx Employee
Xilinx Employee
8,568 Views
Registered: ‎09-20-2012

Re: Data width and deep limitation in block ram(Spartan6)

Hi @fpga35man

 

This configuration uses multiple BRAM primitives (four 18K BRAM), you can check the usage in last page of IP configuration GUI.

 

Untitled.png

 

You can also find the above info in summary.log file located in ipcore_dir folder in project directory.

Thanks,
Deepika.
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