cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
tannous
Observer
Observer
479 Views
Registered: ‎02-26-2009

Difficulty updating the wdata bus of an AXI4-Lite Master

Hello,

I am trying to build a data generator on the PL that sends data on regular intervals directly to PS DDR memory. Everytime a data transfer is complete, the data generator module issues an interrupt, and the PS prints the values of the copied data.

Using Vivado 2019.1, and an Ultra96 MPSOC board (v1), here is the IP Integrator view of the design:

IP Integrator ViewIP Integrator ViewExplanation of the above design follows:

  1. The data_generator module is based on the Vivado AXI4Lite Master template. The main modification is for the write data process. Instead of resetting the axi_wdata every time a new transfer request is issued to the AXI Master, axi_wdata keeps it's value throughout transfers, and monotonically increment its value (think up-counter).
  2. The pulsegenerator_0 module is a custom module (AXI4Lite slave) that generates a two-clock-cycle-wide pulse at a specified frequency.
  3. The data_generator signal m00_axi_txn_done is asserted at the end of every data transfer, and is connected to the pl_ps_irq[0:0] port to generate an interrupt to PS.
  4. The pulsegenerator_0 signal pulse_out is asserted at regular intervals and connected to the m00_axi_init_axi_txn port to trigger a new data transfer from data_generator to PS DDR.

On the PS, a baremetal application configures the interrupt controller accordingly. The triggered ISR prints the data from DDR (locations 0x4000000 through 0x400000C).

The good news:

The system mostly works. In other words, the baremetal application running on the PS (Core-0) prints the data in DDR at regular intervals, and the frequency of the intervals is consistent with the intervale frequency configured in the pulsegenerator_0 module.

The bad news:

The data written to DDR is not incrementing beyond the first transfer as expected. The transfer consists of 4 transactions, with the first wdata value set at 0xAA000000 (default by Xilinx AXI4Lite master IP), and the target address is 0x04000000 (The 1 Gig DDR address for the MPSoC). So the first time the PS is interrupted, the application reads the following:

[Addr] 0x4000000: [Data] 0xAA000000
[Addr] 0x4000004: [Data] 0xAA000001
[Addr] 0x4000008: [Data] 0xAA000002
[Addr] 0x400000C:[Data] 0xAA000003

This is the correct output. The second time the PS is interrupted, the application reads the following:

[Addr] 0x4000000: [Data] 0xAA000000
[Addr] 0x4000004: [Data] 0xAA000001
[Addr] 0x4000008: [Data] 0xAA000002
[Addr] 0x400000C:[Data] 0xAA000003

Since the axi_wdata is expected to keep value across transactions and is monotically incrementing, the expected output is as follows:

[Addr] 0x4000000: [Data] 0xAA000004
[Addr] 0x4000004: [Data] 0xAA000005
[Addr] 0x4000008: [Data] 0xAA000006
[Addr] 0x400000C:[Data] 0xAA000007

Data should be incrementing each and every time the PS is interrupted, but that's not happening when running on hardware. A simulation of the data_generator module using the Xilinx provided bfm model reveals that the axi_wdata bus is indeed incrementing as expected accross transfers. Here is a screenshot from the Vivado simulator (note the bus m00_axi_wdata[31:0] towards the buttom of the signal list):

simulation.png

My question to the forum members is a follow: What am I missing?

Thanks,

0 Kudos
Reply
0 Replies