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tamasgy89
Observer
Observer
15,493 Views
Registered: ‎03-27-2008

Dual-Port BRAM Conflict

Hi,

   I've read that using True Dual Port Block RAMs and Coregenerator, it is possible to access the same memory cell in the same time. I know that in this case the result is considered to be invalid, but I just wonder how is it possible to connect the ports on the same cell. Does this also depend on the internal architecture of a BRAM or can I implement this using only the logic cells? I haven't find a way to write an appropiate VHDL code which would do this interconnection. I mean that in normal case the synthesizer gives an error like "multiple-source on signal 'x'". So how can something like this be implemented?

 

   Thanks in advance,

   Tamas 

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4 Replies
zhex
Xilinx Employee
Xilinx Employee
15,473 Views
Registered: ‎08-07-2007

If you choose Dual-Port BRAM in coregen, you will then have two ports, Port A and Port B. You could connect the addr/data signals seperately to these two ports and then the multi source problem will not be reported.

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tamasgy89
Observer
Observer
15,461 Views
Registered: ‎03-27-2008

   That's Ok, but I'm more interested in the case when this conflict occurs :) . I've made some experience by setting the same address and clock signals on both ports and different data signals (as much as I've heard, it doesen't cause any physical damage). I would like to know the architecture of the Dual Port BRAM and how the ports are interconnected. I haven't found any information on the site...

   Thanks,

   Tamas

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pcurt
Explorer
Explorer
15,458 Views
Registered: ‎04-09-2008

My guess would be that the behavior would be deterministic and that either PORTA, or PORTB would "win."  The internal logic probably isn't much more than a mux that selects between data from porta input, or portb input depending on the state of wrena and wrenb.

 

Test it out with a structural model first.  Then try implementing a simple circuit on an FPGA and use chipscope to see.  Keep in mind that behavior between families and particular silicon revisions/steppings may differ.

 

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mmunkejo
Contributor
Contributor
15,282 Views
Registered: ‎06-12-2008

Hi,

 

I would guess that the architecture of blockRAM is an array of dual port Static RAM cells and that there are two individual address decoders that can access/activate the cells at the same time. SRAM cells are basically two inverters connected in feedback loop so that they are able to stay in a given state as long as the power is on. Search the web for SRAM cell to understand how writing and reading works. Multiport SRAM cells are identical to single port cells, but they have additional gate transistors for each port.

 

It is possible to write VHDL code that results in dual port blockRAM, see the XST userguide for examples.

 

Hope this helps

 

Magne

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