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joe306
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Registered: ‎12-07-2018

Dual Port Ram between PL and PS

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Hello, I have an error I am getting when trying to implement a dual port ram between the PL side and the PS side. I have an ADC RTL module that stores the ADC results into a Block Memory Generator. I use a AXI BRAM IP to connect the PS AXI to the Block Memory Generator:

Block.jpg

Here is the Warning Message:

Message.jpg

Here is the Block Memory Generator setup:

BlockMemGen_Basic.jpg

 

BlockMemGen_PortB.jpg

Here is the AXI BRAM:

AXI_BRAM.jpg

What am I doing wrong? Any ideas?

 

Thank you

Joe

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maps-mpls
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Registered: ‎06-20-2017

Sorry, I don't have time to install 2020.2 right now.  But I took a look at your design.

So this is what I would do:

In an RTL flow, instanticate BRAM controller, dual port BRAM configured correctly connection to the BRAM controller and your ADC, and your ADC interface in a verilog wrapper.  After you get it to synthesize without error, add it to your block diagram as a wrapper.  It's not pretty but I don't know of any reason why it would not work.  After that worry about more detailed functionality.

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maps-mpls
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Registered: ‎06-20-2017

It may not like the 12-bit data interface on one port and the 32-bit (presumably, interface is not expanded) on the other. 

If you need different data and address widths, you may have to infer a BRAM (see UG901) in RTL, and package that up as custom IP. 

Or you could make both the ports of the BRAM the same depth and width, and 0-pad in your RTL.

I haven't tried recently, but back in 2018.3 days, as I recall, this is what I had to do.  It could be something else if you're using a newer version of the tools.

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joe306
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Registered: ‎12-07-2018

 Yes, you are absolutely right. I can easily fix that tomorrow. I will give it a try. 

 

Thank you very much,

Joe

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joe306
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Hello, I padded the 12bits with 20bits of zero:

Block.jpg

Here is the BRAM Properties:

BRAM_Prop.jpg

Here is the Dual Port RAM Properties:

DP_PortB.jpg

I will keep looking for a solution.

 

Thank you

Joe

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maps-mpls
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I don't want to send you on a wild goose chase, but if you are stuck, and all else fails, this is what I would try:

Option A:  Do the padding in your RTL

Option B:  Don't use Block Mememory Generator, create your own.

1.  Create and package IP, based on ram_tdp_rf_rf.v or ram_tdp_rf_rf.vhd in UG901 (you can download the files in docNav via hyperlink), or any other model that suits your needs.   Add parameters and generics to customize width and depth (for Verilog or VHDL)

2.  Instantiate and attach to the block memory controller.

If that doesn't work, and depending on which version of Vivado you're using, you might also instantiate the block memory controller in an RTL flow within the create and package IP.  However, I know this did not used to work, and will only work for you if Xilinx allows you to instantiate IP within a create and package IP project. 

As a last hope, you could modify your RTL (or make a shim between your RTL) to translate from the BRAM interface to an AXI-L or AIX-F interface, and attach the shim to an AXI interconnect, like so:

RTL -> RTL-AXI Shim -> AXI-IC -> BRAM CTRL -> Dual Port BRAM

PS -> AXI-IC (same as above) ^^^

To help with your shim, create and package a dummy AXI-F Master interface, and that will give you template code to use (including naming conventions that Vivado should recognize).  You may have to package your RTL as an IP instead of instantiating it as an RTL module in IPI.

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joe306
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Registered: ‎12-07-2018

Hello, thank you for helping me. I am using a Concat IP to pad the zeros, is that not what you suggest? Should I aave that padding done in the verilog code? Last, seems you think the problem is a data width issue. What do you make out of the warning message, "Bus interface property MASTER_TYPE does not match BRAM_PORTB(OTHER) and BRAM_PORTA(BRAM_CTRL)"? What's this message mean? What would be a better way to send ADC values to the PS side? I thought using a Dual Port would be the way to go?

Thank you very much,

Joe

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maps-mpls
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Registered: ‎06-20-2017

No, there is no reason why it shouldn't work, but a lot of things that should work sometimes require workarounds. 

 

Another option is to instatiate a bram controller, let it autoconnect to a BRAM (both ports) then disconnect one of the ports on the BRAM manually, change the bram controller back to a single port, change the bram generator port you want to your RTL.

 

If I had your design, I could try some simple things.  But that is the nature of the forums.  If you're stuff is good why would you want to post it for the world to see?

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joe306
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Registered: ‎12-07-2018

Here is my project in TCL if you want to try some things. 

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maps-mpls
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Registered: ‎06-20-2017

Thanks.  But if you could create a simplified block diagram with your RTL in question (or a simplified version of your RTL) it would be a lot easier for me.  I just looked through your script and I don't think It will help me.  Open your .bd (or a simiplified one) and do a write_bd_tcl {c:\yourpath\my_bd.tcl}, and upload it with the RTL module (or a simplified version that still produce the problem).

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joe306
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Hello, thank you very much for helping me. Here is what I am trying to do:

DUAL_PORT_APP.jpg

I archived my project and also did the write_bd_tcl. 

Thank you very much for your help.

Joe

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maps-mpls
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Registered: ‎06-20-2017

Sorry, I don't have time to install 2020.2 right now.  But I took a look at your design.

So this is what I would do:

In an RTL flow, instanticate BRAM controller, dual port BRAM configured correctly connection to the BRAM controller and your ADC, and your ADC interface in a verilog wrapper.  After you get it to synthesize without error, add it to your block diagram as a wrapper.  It's not pretty but I don't know of any reason why it would not work.  After that worry about more detailed functionality.

*** Destination: Rapid design and development cycles *** Unappreciated answers get deleted, unappreciative OPs get put on ignored list ***

View solution in original post

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joe306
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Registered: ‎12-07-2018

Thank you very much. I will give that a try. 

 

Joe

joe306
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Registered: ‎12-07-2018

Hello, wanted to post my solution. I changed the BMG to Standalone mode. I then created an AXI Slave Peripheral that can access the Dual Port Ram.

MyTopBlock.jpg

Here is my simulation:

dual_port_axi_sim.jpg

I know there is probably better ways of doing this but it is a start. I have uploaded my project for anyone to see what I did.

Respectfully,

Joe

joe306
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Registered: ‎12-07-2018

I am still a newbie and know I have a lot to learn.

maps-mpls
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It's a fine solution.

*** Destination: Rapid design and development cycles *** Unappreciated answers get deleted, unappreciative OPs get put on ignored list ***
joe306
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Thank you. Sometimes its frustrating trying to learn all this stuff, AXI buses, Timing Closure, Transceivers, HLS, Versal, RFSOC. My eyes are getting worse and I'm not getting any younger. I try to keep up with the younger engineers and its tough. 

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