02-15-2021 06:04 AM - edited 02-16-2021 01:23 AM
This question has already been asked but I can't find an answer. I use Vivado 2020.1 and I try to use a FIFO Distributed RAM from the IP Catalog. I have a problem because the empty and full flags never go to 0 even if the reset signal is disabled. Because of that I can't read in the FIFO. Here is a screenshot of the simulation.
Thanks for your help!
02-15-2021 08:10 AM
These are syncronous FIFO's
The FIFOs need a constant clock on both the read and write clocks,
inside the FIFO are state machines, without a clock they can not run.
02-16-2021 01:57 AM
Can you run the simulation for longer before you provide any data? it looks like the full flag drops at the end of the waveform. Its also not clear what this waveform relates to.
02-16-2021 02:47 AM
The specification of the FIFO states that the read and write clocks need to be constant,
its the enables that you take up and down,
If you turn off one of the clocks, the associated read or write state machine can not run,
and you will get strange results.