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username45
Visitor
Visitor
576 Views
Registered: ‎02-15-2021

Empty and full flag never deasserted - Fifo generator

Hi,

This question has already been asked but I can't find an answer. I use Vivado 2020.1 and I try to use a FIFO Distributed RAM from the IP Catalog. I have a problem because the empty and full flags never go to 0 even if the reset signal is disabled. Because of that I can't read in the FIFO. Here is a screenshot of the simulation.

username45_0-1613398630298.png

Thanks for your help!

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8 Replies
drjohnsmith
Teacher
Teacher
542 Views
Registered: ‎07-09-2009

These are syncronous FIFO's 

The FIFOs need a constant clock on both the read and write clocks,

    inside the FIFO are state machines, without a clock they can not run.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
username45
Visitor
Visitor
480 Views
Registered: ‎02-15-2021

Hi, thank you for your help.

But as you can see on the screenshot there is a clock for each of the read and the write parts (rd_clk and wr_clk).

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richardhead
Scholar
Scholar
471 Views
Registered: ‎08-01-2012

Are you sure you're using vivado 2010.1? The first version I am aware of is 2012.1

Can you post your code?

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username45
Visitor
Visitor
469 Views
Registered: ‎02-15-2021

It's a mistake, I use Vivado 2020.1.

I can attach th code but I use some librairies from Opal Kelly Front Panel.

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richardhead
Scholar
Scholar
460 Views
Registered: ‎08-01-2012

And the testbench used to generate the waveform?

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username45
Visitor
Visitor
459 Views
Registered: ‎02-15-2021

There it is !

I manage the rst thanks to the wire at the end of the Test Bench

Thank you !

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richardhead
Scholar
Scholar
452 Views
Registered: ‎08-01-2012

Can you run the simulation for longer before you provide any data? it looks like the full flag drops at the end of the waveform. Its also not clear what this waveform relates to.

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drjohnsmith
Teacher
Teacher
436 Views
Registered: ‎07-09-2009

The specification of the FIFO states that the read and write clocks need to be constant,

    its the enables that you take up and down,

If you turn off one of the clocks, the associated read or write state machine can not run,

   and you will get strange results.

 

   

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>