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Adventurer
Adventurer
608 Views
Registered: ‎10-16-2012

Error Place 30-640

Hello

i've got errors when create simple project with 8 Aurora Chip2Chip inerfaces

[Place 30-640] Place Check : This design requires more GTHE4_COMMON cells than are available in the target device. This design requires 7 of such cell types but only 6 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.
[Place 30-99] Placer failed with error: 'IO Clock Placer stopped due to earlier errors. Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

I have whole one quad empty, what am I doing wrong?

xdc:

#sdfs
set_property IOSTANDARD LVDS [get_ports {AUR_INITCLK_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {AZP_INITCLK_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {UF_INITCLK_clk_p[0]}]

set_property PACKAGE_PIN T2 [get_ports {AUR_SERIAL_RX_rxp[0]}]
set_property PACKAGE_PIN P2 [get_ports {AUR_SERIAL_RX_rxp[1]}]
set_property PACKAGE_PIN L8 [get_ports AUR_DIFF_REFCLK_clk_p]
set_property PACKAGE_PIN L27 [get_ports AZP1_REFCLK_clk_p]
set_property PACKAGE_PIN L31 [get_ports {AZP1_SERIAL_RX_rxp[0]}]
set_property PACKAGE_PIN K33 [get_ports {AZP1_SERIAL_RX_rxp[1]}]
set_property PACKAGE_PIN J27 [get_ports AZP2_REFCLK_clk_p]
set_property PACKAGE_PIN H33 [get_ports {AZP2_SERIAL_RX_rxp[0]}]
set_property PACKAGE_PIN F33 [get_ports {AZP2_SERIAL_RX_rxp[1]}]
set_property PACKAGE_PIN G27 [get_ports AZP3_REFCLK_clk_p]
set_property PACKAGE_PIN E27 [get_ports AZP4_REFCLK_clk_p]
set_property PACKAGE_PIN E31 [get_ports {AZP3_SERIAL_RX_rxp[0]}]
set_property PACKAGE_PIN D33 [get_ports {AZP3_SERIAL_RX_rxp[1]}]
set_property PACKAGE_PIN C31 [get_ports {AZP4_SERIAL_RX_rxp[0]}]
set_property PACKAGE_PIN B33 [get_ports {AZP4_SERIAL_RX_rxp[1]}]
set_property PACKAGE_PIN C8 [get_ports AZP5_REFCLK_clk_p]
set_property PACKAGE_PIN D2 [get_ports {AZP5_SERIAL_RX_rxp[0]}]
set_property PACKAGE_PIN C4 [get_ports {AZP5_SERIAL_RX_rxp[1]}]
set_property PACKAGE_PIN B10 [get_ports AZP6_REFCLK_clk_p]
set_property PACKAGE_PIN B2 [get_ports {AZP6_SERIAL_RX_rxp[0]}]
set_property PACKAGE_PIN A4 [get_ports {AZP6_SERIAL_RX_rxp[1]}]
set_property PACKAGE_PIN R27 [get_ports UF_REFCLK_clk_p]
set_property PACKAGE_PIN T33 [get_ports {UF_SERIAL_RX_rxp[0]}]
set_property PACKAGE_PIN P33 [get_ports {UF_SERIAL_RX_rxp[1]}]
set_property PACKAGE_PIN P11 [get_ports {AZP_INITCLK_clk_p[0]}]
set_property PACKAGE_PIN Y5 [get_ports {AUR_INITCLK_clk_p[0]}]
set_property PACKAGE_PIN Y8 [get_ports {UF_INITCLK_clk_p[0]}]

thanks for help!!!!

Regards!

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9 Replies
Adventurer
Adventurer
553 Views
Registered: ‎10-16-2012

Re: Error Place 30-640

@pthakare can you help?, i think its software proble

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Moderator
Moderator
480 Views
Registered: ‎01-10-2019

Re: Error Place 30-640

Hi @dkasmin ,

Can you please let me know the complete FPGA part which you are using in the design  .

Thanks,
Rahul Khatri
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Adventurer
Adventurer
464 Views
Registered: ‎10-16-2012

Re: Error Place 30-640

Hi, @rkhatri 

Zynq Ultrascale+   xczu15eg-ffvb1156-2-i

Thanks for helping me

Regards,

dkasmin

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Moderator
Moderator
410 Views
Registered: ‎01-10-2019

Re: Error Place 30-640

Hi @dkasmin ,

The device xczu15eg-ffvb1156-2-I has 24 GT which mean its has 6 GT_common channel . By vivado error message it look like you are using 7 GT_common channel . Due to which vivado tool gives the error .

 

Thanks,
Rahul Khatri
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Adventurer
Adventurer
389 Views
Registered: ‎10-16-2012

Re: Error Place 30-640

hello @rkhatri

in my project i use only 16 GT lanes, look at PDF and xdc. Its software mistake. I can share project to you,if you wanted.

regards,

dkasmin

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Moderator
Moderator
370 Views
Registered: ‎01-10-2019

Re: Error Place 30-640

Hi @dkasmin ,

I saw the PDF which you have attached . You are using axi_chip2chip_0_aurora to axi_chip2chip_7_aurora . I believe you are using the option “share logic in core” for all the IP . When option “share logic is core” is selected then common channel is used in each core.  Due to which vivado gives the error of more GTHE4_COMMON cells required . You can use the option “share logic in example design” .

Thanks,
Rahul Khatri
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Adventurer
Adventurer
354 Views
Registered: ‎10-16-2012

Re: Error Place 30-640

hello, @rkhatri 

i need different REFCLK for single QUAD for simultaneously work with 2 differents axi_chip2chip IP_CORES(e.g. Multiple External Reference Clocks for Single Quad). When i choose include shared logic in example design GTREF_CLK set single ended and i can't take REFCLK from FPGA PIN what i want.

Can you help this it?

Regards,

dkasmin

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Adventurer
Adventurer
264 Views
Registered: ‎10-16-2012

Re: Error Place 30-640

hello, @rkhatri
any help?
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Adventurer
Adventurer
216 Views
Registered: ‎10-16-2012

Re: Error Place 30-640

i think, i found a answer here

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