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nz654321
Newbie
Newbie
288 Views
Registered: ‎08-08-2018

Error on changing Memory Interface Generator PIN Location

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Hi

I'm using MIG IP core for generating DDR3 SDRAM MCB and according to my PCB I have to change Data Pin locations (DQ 0 to 15) but when I change them I get the following errors:

ERROR: Place:1073 - Placer was unable to create RPM[IOB_RPMs] for the component
mcb4_dram_dq<10> of type IOB for the following reason.
The reason for this issue:
Some of the logic associated with this structure is locked. This should cause
the rest of the logic to be locked. A problem was found where we should
place MCB memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/samc_0 off the edge
of the chip in order to satisfy the relative placement requirement of this
logic. The following components are part of this structure:

ERROR: Place:1073 - Placer was unable to create RPM[IOB_RPMs] for the component
mcb4_dram_dq<10> of type IOB for the following reason.
The reason for this issue:
All of the logic associated with this structure is locked and the relative
placement of the logic violates the structure. The problem was found between
the relative placement of IOB mcb4_dram_dq<10> at site PAD456 and IODELAY
memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/dq_15_0_data.iodrp2_DQ_10 at
site IODELAY_X0Y129. The following components are part of this structure:
IOB mcb4_dram_dq<10>
IODELAY
memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/dq_15_0_data.iodrp2_DQ_10

 

and the other errors for other pins are the same.

Can I change the pin locations or not? if yes what should I do about these errors?

I'm using Xc6slx100 FPGA and MT41J128M16 RAM

thanks

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hpbhat
Adventurer
Adventurer
198 Views
Registered: ‎02-08-2021

Hi,

I understand that you are swapping the DQ pins to ease the PCB layout. 

https://www.xilinx.com/support/documentation/user_guides/ug388.pdf

Above is the MIG user guide & page 42 mentions about the pin swap

" DQ bit swapping at the memory interface is permitted to facilitate layout. Swapping should only be done within a data group."

This means, you have to swap the DQ pins within the DQ lane. If this is followed while swapping in the hardware, that is sufficient. On the Vivado project, you can not change the XDC pins but if the swapping is done within DQ lane, the design will work without any issue.

With Regards,

HPB

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hpbhat
Adventurer
Adventurer
199 Views
Registered: ‎02-08-2021

Hi,

I understand that you are swapping the DQ pins to ease the PCB layout. 

https://www.xilinx.com/support/documentation/user_guides/ug388.pdf

Above is the MIG user guide & page 42 mentions about the pin swap

" DQ bit swapping at the memory interface is permitted to facilitate layout. Swapping should only be done within a data group."

This means, you have to swap the DQ pins within the DQ lane. If this is followed while swapping in the hardware, that is sufficient. On the Vivado project, you can not change the XDC pins but if the swapping is done within DQ lane, the design will work without any issue.

With Regards,

HPB

View solution in original post

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