Ethernet SGMII and aurora clock sharing

[raghusrinivas_451993]

Hi,

I am using AXI Ethernet Subsystem IP for SGMII and aurora IP on the same GTH of Artix 7 FPGA. I am configuring Ethernet as core design and sharing the clock to aurora.

When I see in ILA tx_lock is happening but lane_up and channel_up is not happening.

I am also attaching the block design picture for reference

Regards,

Raghu

[shudaizi]

I'm doing the same thing. "sync_clk gose as txuserclk for A7 GTP" ,"user_clk goes as txuserclk2 input to GTP".

So I think they should connect to userclk_out of ethernet subsystem.