01-07-2019 03:12 AM
i have a fifo(512*8) in my design, when full flag fifo is 1, what is the content of wr_data_count and rd_data_count of that?
01-13-2019 12:34 AM
During the continuous writing if FIFO full flag is asserted , the wr_data_count should reach to 512.
are you observing any anomalous behavior than this ? Please share your simulation Screenshot.
01-13-2019 05:10 AM
yes in my implementation, when i inspected my design with ILA core when wr_data_count is abut 300 the full flag is 1 for one clk and in next one go to zero.
01-13-2019 06:17 AM
Can you please attache .ila or ILA screenshot depicting this unusual behaviour?
01-13-2019 07:10 AM
I don't believe you mentioned in your post, does your FIFO use independent clocks? Are you monitoring the signals in question using the clock domain that generated them, the write clock for the full flag and the read clock for the empty flag? For a FIFO with independent clocks, there is an internal clock domain crossing that you need to take into account. Look at the block diagram (figure 3-25) and the Synchronization Considerations section in the product guide for the FIFO Generator IP.