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hrmt
Explorer
Explorer
1,091 Views
Registered: ‎06-09-2018

FIFO Full Flag

Hi everybody

i have a fifo(512*8) in my design, when full flag fifo is 1, what is the content of wr_data_count and rd_data_count of that?

Thanks.

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5 Replies
pthakare
Moderator
Moderator
1,022 Views
Registered: ‎08-08-2017

Hi @hrmt

During the continuous writing if FIFO full flag is asserted , the  wr_data_count should reach to 512.

are you observing any anomalous behavior than this ?  Please share your simulation Screenshot.

 

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hrmt
Explorer
Explorer
1,009 Views
Registered: ‎06-09-2018

yes in my implementation, when i inspected my design with ILA core when wr_data_count is abut 300 the full flag is 1 for one clk and in next one go to zero.

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pthakare
Moderator
Moderator
1,002 Views
Registered: ‎08-08-2017

Can you please attache .ila or ILA screenshot depicting this unusual behaviour?

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bruce_karaffa
Scholar
Scholar
991 Views
Registered: ‎06-21-2017

I don't believe you mentioned in your post, does your FIFO use independent clocks?  Are you monitoring the signals in question using the clock domain that generated them, the write clock for the full flag and the read clock for the empty flag?  For a FIFO with independent clocks, there is an internal clock domain crossing that you need to take into account.  Look at the block diagram (figure 3-25) and the Synchronization Considerations section in the product guide for the FIFO Generator IP.

hayk.petr
Adventurer
Adventurer
967 Views
Registered: ‎10-04-2018

@hrmt use FIFO debug ports such as: Data Count and Status Flags: Amost Full to see what is going on.

Sometimes ILA provides tricky results.

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