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puniths_d
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Registered: ‎07-31-2008

FIFO on powerup shows both empty flag and full flag as '1' in FPGA

hai

 

 i designed a fifo for spartan 3e. i nthe simulation the empty flag is 1 and full flag is 0 upon starting . when i  configured it in the fpga it shows both flag as '1'. i also checked the reset . the fifo is not under reset condition. the clock to the fifo is also good.  I have used the  xilinxs core  generator fifo 3.3 . i have used common clock bulit in RAM. can any body help  regarding this ?

thanks

punitha  

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