FIFO on powerup shows both empty flag and full flag as '1' in FPGA
i designed a fifo for spartan 3e. i nthe simulation the empty flag is 1 and full flag is 0 upon starting . when i configured it in the fpga it shows both flag as '1'. i also checked the reset . the fifo is not under reset condition. the clock to the fifo is also good. I have used the xilinxs core generator fifo 3.3 . i have used common clock bulit in RAM. can any body help regarding this ?