07-05-2013 02:06 AM
I'm trying to implement an ansychronous fifo. The goal is to shift data in very fast and then read out when it's needed and refill when necessary.
The problem is that as far as write works ok, I observe ~6 read clock cycles latency for read operation
How do i get rid of latency? The read frequency is low, but the timing accuracy is critical, so i cannot afford to cycle trough first few record in order for the data to get valid.
What am I doing wrong?
07-05-2013 03:27 AM
If you know that you will never be writing and reading from the FIFO simultaneously, then you do not need the Xilinx FIFO function and its considerable overhead. Just use a dual-port RAM, with your own controller logic. This will reduce the initial read latency considerably, to as little as one (read) clock cycle.
-- Bob Elkind
07-05-2013 06:33 AM
If you want to use the Xilinx coregen FIFO, you can't have clocks that stop as in your first
waveform for write clock. The flag synchronization works on both clocks, so if either
clock stops the empty flag will not propagate to the output pin.
In your second waveform, I don't see the write related signals. Your "six clock latency" is
mostly while the empty flag is asserted, which may or may not be due to the write clock stopping.
Once the empty flag deasserts, the read latency is one cycle.
10-30-2013 02:23 AM