cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
chennan
Visitor
Visitor
9,523 Views
Registered: ‎06-06-2013

FIFO simulation problem

Hi,

I am simulating a FIFO in my design with structural model. However, in the simulation, the dout remains XXX even if the empty flag indicates that the data is written into the FIFP. Here is the timing table in the simulation. I think I must made some very stupid mistake since this is the first time I use FIFO. Please help me!

Thanks!

Chennan

whole timing diagram.jpg
zoom in around 54ms.jpg
0 Kudos
2 Replies
chennan
Visitor
Visitor
9,520 Views
Registered: ‎06-06-2013

Here is the setting of the FIFO

parameters.jpg
0 Kudos
balkris
Xilinx Employee
Xilinx Employee
9,006 Views
Registered: ‎08-01-2008

You need to check the warning generated by tool. It seems all the output data are XXX. this only meant core is not instant properly or your project corrupted any how
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos