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masken
Visitor
Visitor
11,488 Views
Registered: ‎08-26-2009

FIFO synchronization

Hi,

 I want to connect one side of a FIFO (from core generator implemented in spartan 3A) to an asyncronuos bus (without clock).

The bus transfers are directly related to the edges of the read and write signals.

My plan is to feed the FIFO with a clock signal several times faster than the bus frequency (~10MHz) to get a FIFO

that from an outside perspective seems to have no clock.

I understand that the clock frequeny must be chosen high enough to satisfy the timing of the bus,

but what else criterias should be met?

Should I for example latch all data and control inputs on the FIFO with the clock signal?

I hope someone understands the situation, I am pretty much a newbie when i comes to FPGA's and apreciate all comments!

 

Mats

 

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luisb
Xilinx Employee
Xilinx Employee
10,804 Views
Registered: ‎04-06-2010

This is going to depend on the type of FIFO you're using. Are you implementing you're own FIFO? Or are you using CoreGen to create you're FIFO? If you're using CoreGen, then what type of FIFO? BRAM, dedicated FIFO, LUTs, Shift Registers?
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masken
Visitor
Visitor
10,800 Views
Registered: ‎08-26-2009

I am using CoreGen with blockram in a Spartan-3A.

The solution was to oversample the signals and wait for two identical states of the signal before changing the internal representation of the signal. It seems to work fine.

Any feedback on this solution is appreciated.

 

process()

  if (presyncRead = '1') and (ReadPin = '1') then
        syncRead <= '1';
    if (presyncRead = '0') and (ReadPin = '0') then 
        syncRead <= '0';
    end if;
    presyncRead  <= ReadPin;

end process;

 

 

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luisb
Xilinx Employee
Xilinx Employee
10,791 Views
Registered: ‎04-06-2010

If you read the FIFO Generator User Guide it state that the synchronization is done for you when you select independent clocks.  Look at the bottom of page 43.

 

http://www.xilinx.com/support/documentation/ip_documentation/fifo_generator_ug175.pdf

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