08-26-2009 01:45 AM
I want to connect one side of a FIFO (from core generator implemented in spartan 3A) to an asyncronuos bus (without clock).
The bus transfers are directly related to the edges of the read and write signals.
My plan is to feed the FIFO with a clock signal several times faster than the bus frequency (~10MHz) to get a FIFO
that from an outside perspective seems to have no clock.
I understand that the clock frequeny must be chosen high enough to satisfy the timing of the bus,
but what else criterias should be met?
Should I for example latch all data and control inputs on the FIFO with the clock signal?
I hope someone understands the situation, I am pretty much a newbie when i comes to FPGA's and apreciate all comments!
05-19-2010 08:41 PM
05-19-2010 09:27 PM
I am using CoreGen with blockram in a Spartan-3A.
The solution was to oversample the signals and wait for two identical states of the signal before changing the internal representation of the signal. It seems to work fine.
Any feedback on this solution is appreciated.
if (presyncRead = '1') and (ReadPin = '1') then
syncRead <= '1';
if (presyncRead = '0') and (ReadPin = '0') then
syncRead <= '0';
presyncRead <= ReadPin;
05-20-2010 06:51 AM
If you read the FIFO Generator User Guide it state that the synchronization is done for you when you select independent clocks. Look at the bottom of page 43.