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mike_56
Newbie
Newbie
3,436 Views
Registered: ‎02-14-2018

FIFO with UltraRam

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Hi,

I'm currently estimating the FPGA resources utilization for a future project based on an UltraScale+.

I'm wandering if there is any Xilinx IP to generate FIFO based on UltraRam memory :

-Is there any plan to support UltraRam in the FIFO generator IP ? (from my understanding, only Block RAM, Distributed RAM and Sift register are currently supported).

-Is there any other solution to generate a FIFO based on UltraRam ?

 

Thanks in advance for our answers.

Regards

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vemulad
Xilinx Employee
Xilinx Employee
3,624 Views
Registered: ‎09-20-2012

Hi @mike_56

 

Please close the thread by marking the answer.

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
3,390 Views
Registered: ‎09-20-2012

Hi @mike_56

 

The FIFO generator IP does not support URAM based FIFO.

 

You have to use XPM_FIFO. Refer to https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug974-vivado-ultrascale-libraries.pdf for more details.

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
mike_56
Newbie
Newbie
3,382 Views
Registered: ‎02-14-2018

Hi @Deepika,

 

Thank you very much for your answer.

 

Best Regards

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vemulad
Xilinx Employee
Xilinx Employee
3,625 Views
Registered: ‎09-20-2012

Hi @mike_56

 

Please close the thread by marking the answer.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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