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Participant
Participant
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Registered: ‎09-04-2019

FPGA SIDE JESD RX sync not asserted

Hi,

I am using JESD 4 lanes configuration for TX and RX on ZCU111 with TI AFE76xx.

Link parameters are as follows :LMFS - 4421 TX/RX, Linerate = 7.372 gbps, refclk = 368.64MHz, JESDcoreclk= linerate/40, sysref = 15.36MHz. Syref and Devclk are same at AFE side also.

I am able to establish connection with TX, as I could see tx_sync is asserted high passing JESD phases(CGS,ILA) but with RX path, sync which is going to AFE is forever low. In the design I have 2 phy jesd cores each with 2 lanes of RX & TX. I am not sure whether CGS phase is happening or whereit might've gone wrong.

Here I have attached some free run snaps of RX JESD signals on ILA.

Cjesd_afe.JPGJesd_afe1.JPG

 

Regards,

Rakshi

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Observer
Observer
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Registered: ‎05-24-2020

@raksssss 

Did you take it up with TI ? You may want to try posting on https://e2e.ti.com/support/data-converters . They will help you with configuring the ADC.

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Participant
Participant
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Registered: ‎09-04-2019

Hi @raj,

I am yet to take help from TI. Thanks for the response.

I saw your other detailed post about rx losing sync, which got me so much insights about JESD. Thanks for this.But I have one doubt, how do I read status registers in run time which helps in debugging and which is accessable via AXI-4 lite of JESD? Should it be RTL logic controlled( which I feel not easy) or Can be accessed from PS without have to worrying about controlling through RTL logic, if yes how it should be done ? 

regards,

Rakshi

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Observer
Observer
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Registered: ‎05-24-2020

@raksssss 

Please verify -
1) JESD parameters on FPGA and ADC match (eg - K, F, scrambling, etc)

2) Clock frequency to the ADC and FPGA. Check the divider values on the LMK chip if using LMK.

3) Get the clocks to the FPGA up and running before programming the FPGA.

4) Hold the FPGA in reset and program the ADC. Then clear the reset.

5) Check if CPLL or QPLL is locked. Also check if resetdone is high.

Are you using "Shared logic in core" or "Shared logic in Example" ? Depending on the configuration, check PG066 or PG198 for AXI register addresses.

For reading/writing AXI registers, you can do it in software or if you don't want to take that long route, you may want to use "JTAG to AXI Master" IP (https://www.xilinx.com/support/documentation/ip_documentation/jtag_axi/v1_2/pg174-jtag-axi.pdf ). This will give you access to AXI registers without having to write software in PS. I use JTAG to AXI IP in my design.

If you decide to use JTAG to AXI, you can do the following -

1) Create a custom AXI IP to write to rx_reset pin of JESD RX module. Add this custom IP to your block design.

2) Add JTAG to AXI master IP to block design.

3) Note the addresses of JESD RX module and your custom AXI IP in Address editor.

4) After you program the FPGA, you can use these example commands in Tcl console to access the registers. You can also refer to PG174 for JTAG to AXI master IP usage.

#Read Debug status 0x03C register (PG066 Table 2-14)
create_hw_axi_txn rd_rxdbgsts [get_hw_axis hw_axi_1] -address 8000003C -type read 

#Read Link error status 0x01C register
create_hw_axi_txn rd_rxlnkerrsts [get_hw_axis hw_axi_1] -address 8000001C -type read

#Write 1 to bit 0 of error reporting 0x034 register
create_hw_axi_txn wr_rxerren [get_hw_axis hw_axi_1] -address 80000034 -data 00000001 -type write

Note- in the example, the JESD RX module address is 80000000.

To run these above commands you can write "run_hw_axi rd_rxdbgsts rd_rxlnkerrsts wr_rxerren" in the Tcl console.

Here is the initialization sequence I am following - 

1) Program LMK and wait for PLL2 Lock.

2) Program FPGA

3) Send 1 to rx_reset pin of the JESD RX module.

4) Send 0 to rx_reset pin of JESD RX module.

5) Write 0x2 to JESD RX AXI register 0x04 (fixed reset) to hold the JESD core in reset.

6) Program ADC registers.

7) Clear JESD core reset. After clearing reset, the GT lanes start seeing 0xBCBC characters.

Trigger Sysref

 

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Observer
Observer
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Registered: ‎05-24-2020

@raksssss 

Also check Sysref freq. It should be = Fs/(K*N), where N is an integer.

Are you using continuous sysref or pulsed ?

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Participant
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Registered: ‎09-04-2019

@raj Thanks for the detailed explanation on JTAG to AXI master IP which I was not aware of. For sure, this IP would be useful to interact with AXI interfaces of certain IP's, will definitely try this.

Regarding JESD,

1. We are trying out LMFS -2221 and 4421. Lane rate was different at fpga, now it is 9.8 Gbps with core clk = 245.76Mhz. Now atleast, after complete init I see CGS characters on RX lanes with rx_sync high. perhaps it might be issue with sequence/any other have to debug further. I have to try out the sequences specially with reset and programming ADC. In general, should the transmitter to be configured first then later receiver in JESD link bring up? Please, comment your views on this point.

2. Ref_clk to AFE and FPGA JESDPHY PLL is same which is equal to 368.64 MHz and sysref is 15.36MHz periodic and continuous mode(subclass 1)

3. First step after FPGA is programmed is to get the clocks and sysref up (LMK source) and have probed, it is fine.

4. I am using software controlled AXI_GPIO one bit for reset. Based on this event, I internally generate common JESD reset which is issued to JESD RX/TX(rx/tx_reset) for some duration and followed by JESDPHY reset(sysrst). 

5. After the clock is up and reset process is complete,I could see reset_done and qpll_lock asserted.

6. I have 2 JESD cores for Tx and RX with shared logic in example design and one PHY(TX_RX) core with shared logic in core. So, AXI4-lite of JESD TX/RX core is active and is to be accessed via JTAG AXI master I guess. pls,confirm my understanding. 

7. SYSREF = 491.52 MSPS/ 32 x 1  = 15.36 MHZ for N = 1.

Also, would like to know in your case - with HW_eval license,was it only RX losing sync ? what about TX ?

Thanks & Regards,

Rakss

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Observer
Observer
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Registered: ‎05-24-2020

@raksssss 
1. Yes, configure transmitter before configuring receiver.
6. Yes, you will have to access JESD_RX and JESD_TX modules via JTAG AXI and some of the signals in JESD_PHY will be available as external IO pins on the module.

In my case, with Hardware evaluation license caused both JESD modules (RX and TX) to go down after a certain time. In JESD_RX module, the rx_sync signal went low and in JESD_TX module, the tx_ready signal went low causing the links to go down.

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Participant
Participant
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Registered: ‎09-04-2019

Hi @raj,

Thanks for the reply. I would like to confirm the same license thing on JESD, which is getting seized after 1hr 45 min appx. Can you confirm this is this because of HW_EVAL license? (tx_tready signal I don't have it in ILA)

RX lane data is not there in this particular screenshot, this was taken before proper RX config happened, not taken any other screenshots, but data will be there on latest designs.

After this stage, CGS characters are pushed onto the TX_RX lanes with tx sync = 1'b1 and rxsync = 1'b0 indefinetly.

Link doesn't respond to any reset/ resync/re-init, only option is restarting/reprogramming fpga.

raksssss_0-1600693849704.jpeg

Regards,

Rakss

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Observer
Observer
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Registered: ‎05-24-2020

@raksssss If you're seeing repeatable behavior that may be because of Evaluation license. Are you using evaluation license or purchased ?
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