cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
367 Views
Registered: ‎05-12-2018

Fast-Fourier-Transform IP 9.1 no autogenrated VHDL testbench?

Jump to solution

As stated in the doc PG-109 , Page 85 - there is supposed to be an autogenerated testbench when we generate the FFT IP core.

After synthesis of my design -  I see no demo_tb/tb_<component_name>.vhd file in the <compoent_name>.runs/ folder.

.
├── design_1_xfft_0_0_synth_1
│ ├── design_1_xfft_0_0.dcp
│ ├── design_1_xfft_0_0.tcl
│ ├── design_1_xfft_0_0_utilization_synth.pb
│ ├── design_1_xfft_0_0_utilization_synth.rpt
│ ├── design_1_xfft_0_0.vds
│ ├── dont_touch.xdc
│ ├── gen_run.xml
│ ├── htr.txt
│ ├── ISEWrap.js
│ ├── ISEWrap.sh
│ ├── project.wdf
│ ├── rundef.js
│ ├── runme.bat
│ ├── runme.log
│ ├── runme.sh
│ ├── __synthesis_is_complete__
│ ├── vivado.jou
│ └── vivado.pb
├── impl_1
│ ├── design_1_wrapper_61683.backup.vdi
│ ├── design_1_wrapper.dcp
│ ├── design_1_wrapper_drc_opted.pb
│ ├── design_1_wrapper_drc_opted.rpt
│ ├── design_1_wrapper_drc_opted.rpx
│ ├── design_1_wrapper.hwdef
│ ├── design_1_wrapper_opt.dcp
│ ├── design_1_wrapper.tcl
│ ├── design_1_wrapper.vdi
│ ├── gen_run.xml
│ ├── htr.txt
│ ├── init_design.pb
│ ├── ISEWrap.js
│ ├── ISEWrap.sh
│ ├── opt_design.pb
│ ├── place_design.pb
│ ├── project.wdf
│ ├── rundef.js
│ ├── runme.bat
│ ├── runme.log
│ ├── runme.sh
│ ├── vivado_61232.backup.jou
│ ├── vivado_61683.backup.jou
│ ├── vivado.jou
│ └── vivado.pb
└── synth_1
├── design_1_wrapper.dcp
├── design_1_wrapper.tcl
├── design_1_wrapper_utilization_synth.pb
├── design_1_wrapper_utilization_synth.rpt
├── design_1_wrapper.vds
├── dont_touch.xdc
├── gen_run.xml
├── htr.txt
├── ISEWrap.js
├── ISEWrap.sh
├── project.wdf
├── rundef.js
├── runme.bat
├── runme.log
├── runme.sh
├── __synthesis_is_complete__
├── vivado.jou
└── vivado.pb

 

 

 <compoent_name>.runs folder structure is shown above. <compoent_name>.ip_user_files/ does not have the mentioned vhd file too.  

I am unable to find the vhdl testbench anywhere in the project folder - even after place_design. The only place I find some mention of it is in : <Xilinx Install dir>/2019.1/data/ip/xilinx/xfft_v9_0/ttcl/testbench_vhdl.ttcl, which is encrypted.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
280 Views
Registered: ‎08-01-2007

You are correct, when FFT IP is added to the bd design, the generated outputs of FFT IP does not have the demo test bench.

If you want to get the demo test bench of FFT IP, open Vivado IP Catalog, find FFT IP, click "customize IP", Configure IP, then click "okay" to generate IP, you can get the demo test bench.

---------------------------------------------------------------------------------
Please Kudo or Accept as a solution, If this Post helped you.
---------------------------------------------------------------------------------

View solution in original post

5 Replies
Highlighted
Moderator
Moderator
362 Views
Registered: ‎08-01-2007

The demo_tb/tb_<component_name>.vhd file is geneated along with the IP, so, when you have configure FFT IP parameters and click okay to generate the IP, after the IP generation is completed, you can find the demo test bench, which should be located in the generated IP directory.

---------------------------------------------------------------------------------
Please Kudo or Accept as a solution, If this Post helped you.
---------------------------------------------------------------------------------

0 Kudos
Highlighted
336 Views
Registered: ‎05-12-2018

Sadly, no - I couldn't find it after generating the block design per IP.

.
├── bd
│   └── design_1
│   ├── ip
│   │   └── design_1_xfft_0_0
│   │   ├── design_1_xfft_0_0_sim_netlist.v
│   │   ├── design_1_xfft_0_0_sim_netlist.vhdl
│   │   └── sim
│   │   └── design_1_xfft_0_0.vhd
│   └── sim
│   ├── design_1.protoinst
│   └── design_1.v
├── README.txt
└── sim_scripts
└── design_1
├── activehdl
│   ├── compile.do
│   ├── design_1.sh
│   ├── design_1.udo
│   ├── file_info.txt
│   ├── glbl.v
│   ├── README.txt
│   ├── simulate.do
│   └── wave.do
├── ies
│   ├── design_1.sh
│   ├── file_info.txt
│   ├── glbl.v
│   ├── README.txt
│   └── run.f
├── modelsim
│   ├── compile.do
│   ├── design_1.sh
│   ├── design_1.udo
│   ├── file_info.txt
│   ├── glbl.v
│   ├── README.txt
│   ├── simulate.do
│   └── wave.do
├── questa
│   ├── compile.do
│   ├── design_1.sh
│   ├── design_1.udo
│   ├── elaborate.do
│   ├── file_info.txt
│   ├── glbl.v
│   ├── README.txt
│   ├── simulate.do
│   └── wave.do
├── README.txt
├── riviera
│   ├── compile.do
│   ├── design_1.sh
│   ├── design_1.udo
│   ├── file_info.txt
│   ├── glbl.v
│   ├── README.txt
│   ├── simulate.do
│   └── wave.do
├── vcs
│   ├── design_1.sh
│   ├── file_info.txt
│   ├── glbl.v
│   ├── README.txt
│   └── simulate.do
├── xcelium
│   ├── design_1.sh
│   ├── file_info.txt
│   ├── glbl.v
│   ├── README.txt
│   └── run.f
└── xsim
├── cmd.tcl
├── design_1.sh
├── file_info.txt
├── glbl.v
├── protoinst_files
│   └── design_1.protoinst
├── README.txt
├── vhdl.prj
└── vlog.prj

 

0 Kudos
Highlighted
Moderator
Moderator
322 Views
Registered: ‎08-01-2007

I'm petty sure the demo test bench is there. Assume you create a vivado project named "project_1". Assume the FFT IP core is named "xfft_0", the FFT IP demo test bench is located at \project_1.srcs\sources_1\ip\xfft_0\demo_tb.

 

---------------------------------------------------------------------------------
Please Kudo or Accept as a solution, If this Post helped you.
---------------------------------------------------------------------------------

0 Kudos
Highlighted
310 Views
Registered: ‎05-12-2018

.
├── design_1.bd
├── design_1.bxml
├── design_1_ooc.xdc
├── hdl
│   └── design_1_wrapper.v
├── hw_handoff
│   ├── design_1_bd.tcl
│   └── design_1.hwh
├── ip
│   └── design_1_xfft_0_0
│   ├── design_1_xfft_0_0.dcp
│   ├── design_1_xfft_0_0_ooc.xdc
│   ├── design_1_xfft_0_0_sim_netlist.v
│   ├── design_1_xfft_0_0_sim_netlist.vhdl
│   ├── design_1_xfft_0_0_stub.v
│   ├── design_1_xfft_0_0_stub.vhdl
│   ├── design_1_xfft_0_0.xci
│   ├── design_1_xfft_0_0.xml
│   ├── sim
│   │   └── design_1_xfft_0_0.vhd
│   └── synth
│   └── design_1_xfft_0_0.vhd
├── ipshared
│   ├── 1123
│   │   └── hdl
│   │   └── xbip_utils_v3_0_vh_rfs.vhd
│   ├── 1971
│   │   └── hdl
│   │   └── axi_utils_v2_0_vh_rfs.vhd
│   ├── 3c11
│   │   └── hdl
│   │   └── xfft_v9_1_vh_rfs.vhd
│   ├── 5204
│   │   └── hdl
│   │   └── cmpy_v6_0_vh_rfs.vhd
│   ├── 7468
│   │   └── hdl
│   │   └── xbip_pipe_v3_0_vh_rfs.vhd
│   ├── 910d
│   │   └── hdl
│   │   └── xbip_dsp48_addsub_v3_0_vh_rfs.vhd
│   ├── cbe4
│   │   └── hdl
│   │   └── c_addsub_v12_0_vh_rfs.vhd
│   ├── cd8a
│   │   └── hdl
│   │   └── c_shift_ram_v12_0_vh_rfs.vhd
│   ├── cdbf
│   │   └── hdl
│   │   └── xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
│   ├── cfdd
│   │   └── hdl
│   │   └── xbip_addsub_v3_0_vh_rfs.vhd
│   ├── d367
│   │   └── hdl
│   │   └── xbip_bram18k_v3_0_vh_rfs.vhd
│   ├── d4d2
│   │   └── hdl
│   │   └── mult_gen_v12_0_vh_rfs.vhd
│   ├── e8d9
│   │   └── hdl
│   │   └── floating_point_v7_0_vh_rfs.vhd
│   ├── ecb4
│   │   └── hdl
│   │   └── c_mux_bit_v12_0_vh_rfs.vhd
│   └── edec
│   └── hdl
│   └── c_reg_fd_v12_0_vh_rfs.vhd
├── sim
│   ├── design_1.protoinst
│   └── design_1.v
├── synth
│   ├── design_1.hwdef
│   └── design_1.v
└── ui
└── bd_1f5defd0.ui

This is the output of ~/workspace/PHOTONIC/FFT-vivado/project_2_FFT_trash/project_2_FFT_trash.srcs/sources_1/bd/design_1 

0 Kudos
Highlighted
Moderator
Moderator
281 Views
Registered: ‎08-01-2007

You are correct, when FFT IP is added to the bd design, the generated outputs of FFT IP does not have the demo test bench.

If you want to get the demo test bench of FFT IP, open Vivado IP Catalog, find FFT IP, click "customize IP", Configure IP, then click "okay" to generate IP, you can get the demo test bench.

---------------------------------------------------------------------------------
Please Kudo or Accept as a solution, If this Post helped you.
---------------------------------------------------------------------------------

View solution in original post