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Adventurer
Adventurer
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Registered: ‎12-09-2010

Feature Request: Assign Clocks to Port Signals of IP Cores

I'm working with the IP integerator and wanted to mark a signal for debugging. If there is no clock assiciated with the port then the tool is not able to determine the clock automatically and the user has to select one. The JESD204 PHY IP core for example does have 6 clock signals and it is not always obvious which signal is clocked by which clock.

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