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h_corey
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Registered: ‎12-24-2009

Fifo IP showing empty, almost empty, almost full, and overflow all at once

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I have a fifo IP instantiated on both my VU9 and V7690T.  It crosses a slow AXI time domain and a fast algorithm time domain.  I am turning the clock rate on my algorithm up.  At a point on both designs the fifo looks normal after boot.  (empty, almost empty only)  When I start the algorithm processing, the empty, almost empty, almost full, and overflow go high all at once.  I have double checked my power usage and at steady state it should be fine.  I am also monitoring my VCCINT voltage via on chip monitoring.  Is this behavior indicative of a large transient on VCCINT?  or something more simple?

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coreyhahn
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Registered: ‎09-13-2018

Found my problem.  Nothing so complicated.  I need to hold reset down for more than 3 clock cycles to fully reset the fifo.  Just like the UG says.  I was only pulsing reset for 1 clock cycle.

 

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coreyhahn
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762 Views
Registered: ‎09-13-2018

Found my problem.  Nothing so complicated.  I need to hold reset down for more than 3 clock cycles to fully reset the fifo.  Just like the UG says.  I was only pulsing reset for 1 clock cycle.

 

View solution in original post

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